16X24B Search Results

16X24B

Abstract: CF160 PF100 PF144 PL84 CPGA Package Diagram
Contextual Info: 16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

PL84

Abstract: ql16x24bl PF100 PF144
Contextual Info: 16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and

QL4090

Abstract: pASIC 1 Family 160CQFP 208-CQFP
Contextual Info: 16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

16X24

Contextual Info: 16x24B/16x24BH WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B pASIC HIGHLIGHTS B Very High Speed - V iaL ink metal-to-metal program m able-via anti­ fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

ix 2933

Abstract: transistor quang 7400 TTL ix 2933 data sheet schematic XOR Gates 7400 chip 7400 series pin connection CF160 schematic diagram inverter PF100
Contextual Info: QuickWorks User's Guide with SpDE™ Reference June 1996 Copyright Information Copyright 1991-1996 QuickLogic Corporation. All rights reserved. The information contained in this manual and the accompanying software program are protected by copyright; all rights are reserved by QuickLogic Corporation.

QuickLogic ql16x24b-1pl84c

Abstract: QL16X24B PF144 cmos io QL16X24BH TQFP 144 PACKAGE CF160 PF100 PL84
Contextual Info: 16x24B/16x24BH Wild Cat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B .4000 usable gates, 122 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

81c78

Abstract: 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference
Contextual Info: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35C 2148-35M 2148-45C 2148-45C 2148-45M 2148-45M+ 2148-55C 2148-55C 2148-55M 2149-35C 2149-35C 2149-35M 2149-45C 2149-45M 2149-45M 2149-55C 2149-55C 2149-55M

68-PIN

Abstract: 84-PIN cpga pinout 208-pin cpga
Contextual Info: Military 5.0V pASIC 1 Family Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA Military 5.0V pASIC 1 Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features Very High Speed • ViaLink“ metal-to-metal programmable technology, allows counter speeds over 150 MHz and

Contextual Info: 16x24B Wildcat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev A pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. B High Usable Density - A 16-by-24 array of384 logic cells provides 12,000

pASIC 1 Family

Abstract: GAL programmer schematic QL24X32B QL12X16B QL16X24B QL8X12B pASIC1 h12k
Contextual Info: pASIC 1 FAMILY ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Very High Speed - ViaLink metal-to-metal, programmable-via anti­ fuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays o f under 2 ns.

CF160

Abstract: PF100 PF144 PL84
Contextual Info: 16x24B 5.0V pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns at 5V, and over 80 MHz at 3.3V operation.

Contextual Info: QL8X12B WildCaX 1000 Very-High-Speed IK 3K Gate CMOS FPGA pASIC HIGHLIGHTS Q Very-High-Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz with logic cell delays of under 2 ns. Q High Usable Density - An 8-by-12 array of 96 logic cells provides 3000

Contextual Info: 16X24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins S 5V Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and bipolar devices by sinking up to 12 mA see IIH specification . S High Usable Density - A 16-by-24 array of 384 logic cells

CPGA144

Contextual Info: 16X24B pASIC 1 FAMILY Very-High-Speed 4K 12K Gate CMOS FPGA PRELIMINARY DATA pASIC HIGHLIGHTS .4000 usable gates, 122 input pins B Very High Speed - ViaLink metal-to-metal programmable-via anti­ fuse technology, allows data path speeds over 150 MHz, and logic cell

Contextual Info: QL12x16B W ildCat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. B High Usable Density - A 12-by-16 array of 192 logic cells provides 6000

Contextual Info: QL8X12B W ildCat 1000 Very-High-Speed IK 3K Gate CMOS FPGA Rev A pASIC HIGHLIGHTS Eg Very High Speed - V iaL ink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 M Hz and logic cell delays of under 2 ns. Q High Usable Density - An 8-by-12 array of 96 logic cells provides 3,000

Contextual Info: QL8x12B WildCat 1000 Very-High-Speed IK 3K Gate CMOS FPGA pASIC HIGHLIGHTS Very-High-Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz with logic cell delays of under 2 ns. B High Usable Density - An 8-by-12 array o f 96 logic cells provides 3000

Contextual Info: 16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and

Contextual Info: pASIC 1 FAMILY ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Q Very High Speed - ViaLink metal-to-metal, programmable-via anti­ fuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays o f under 2 ns.

Contextual Info: QL24x32B WildCat 8000 Very-High-Speed 8K 24K Gate CMOS FPGA ADVANCE DATA pASIC HIGHLIGHTS Cl Very High Speed - ViaLink metal-to-metal program m able-via anti­ fuse technology, allows counter speeds over 150 M Hz and logic cell delays of under 2 ns. B High Usable Density - A 24-by-32 array o f768 logic cells provides 24,000

GAL programmer schematic

Abstract: P/N146071
Contextual Info: pASIC 1 FAMILY ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Q Very High Speed - ViaLink metal-to-metal, programmable-via anti­ fuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.

Contextual Info: QL8X12B WildCaX 1000 Very-High-Speed IK 3K Gate CMOS FPGA Rev A B antifuse technology, allow s co u n ter speeds o v er 150 M H z and logic cell delays o f un d er 2 ns. Q .1000 usable gates, 64 I/O pins Very High Speed - V ia L in k m etal-to-m etal p ro g ra m m a b le-v ia

Contextual Info: 16x24B/16x24BH W ildcat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B P Very High Speed - V ia L in k inetal-to-metal programmable-via anti­ fuse technology, allows counter speeds over 150 M H z and logic cell delays of under 2 ns. d .4000

208-pin cpga

Contextual Info: Military 5.0V pASIC 1 Family Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA last updated 5/15/2000 Military 5.0V pASIC 1 Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features Very High Speed • ViaLink“ metal-to-metal programmable technology, allows counter speeds over 150 MHz and