TRC 817 Search Results

LH52256C-70LL

Abstract: LH52256C
Contextual Info: LH52256C/CH FEATURES • 32,768 x 8 bit organization • Access time: 70 ns MAX. CMOS 256K (32K × 8) Static RAM PIN CONNECTIONS TOP VIEW 28-PIN DIP 28-PIN SK-DIP 28-PIN SOP • Supply current: Operating: 45 mA (MAX.) 10 mA (MAX.) (tRC, tWC = 1 µs) Standby: 40 µA (MAX.)

Contextual Info: Data Sheet, Rev 1.21, June 2006 HYB18L512160BF-7.5 HYE18L512160BF-7.5 DRAMs for Mobile Applications 512-Mbit Mobile-RAM Mobile-RAM RoHS compliant Memory Products Edition 2006-05 Published by Qimonda AG, Am Campeon 10-12, 81726 München, Germany Qimonda AG 2006.

Hitachi DSA00164

Abstract: Nippon capacitors
Contextual Info: HB56AW1672E-A Series 16777216-word x 72-bit High Density Dynamic RAM Module ADE-203-817A Z Rev. 1.0 Aug. 20, 1997 Description The HB56AW1672E-A belongs to 8-byte DIMM (Dual in-line Memory Module) family, and has been developed an optimized main memory solution for 4 and 8-byte processor applications. The

Nippon capacitors

Contextual Info: HB56AW1672E-A Series 16777216-word x 72-bit High Density Dynamic RAM Module HITACHI ADE-203-817A Z Rev. 1.0 Aug. 20, 1997 Description The HB56AW1672E-A belongs to 8-byte DIMM (Dual in-line Memory Module) family, and has been developed an optimized main memory solution for 4 and 8-byte processor applications. The

NT-1/4-0-SP-CS5480

Contextual Info: 16 M DRAM DATA COLLECTION 4 M-word by 4-bit, Revision A 1997 Document No. M12205XJ1V0IF00 1st edition Date Published January 1997 N Printed in Japan DRAM PROCESS 1 DIE PHOTOGRAPH 2 DIFFERENCES BETWEEN REVISION A AND REVISION L 3 µPD42S16405L, 4216405L

Contextual Info: Information 16M DRAM DATA COLLECTION 1M-word by 16-bit, Revision P Document No. M12824XJ1V0IF00 1st edition Date Published September 1997 N 1997 Printed in Japan [MEMO] 2 SUMMARY OF CONTENTS CHAPTER 1 DRAM PROCESS .

Contextual Info: Information 16 M DRAM DATA COLLECTION 2M-word by 8-bit, Revision P Document No. M12859XJ1V0IF00 1st edition Date Published September 1997 N 1997 Printed in Japan [MEMO] 2 SUMMARY OF CONTENTS CHAPTER 1 DRAM PROCESS .

HY51V18164B

Contextual Info: «HYUNDAI HY51V18164B Series 1M X 16-bit CMOS DRAM with Extended Data Out DESCRIPTION The HY51V18164B is the new generation and fast dynamic RAM organized 1,048,576 x 16-bit. The HY51V18164B utilizes Hyundai's CM O S silicon gate process technology as well as advanced circuit techniques

RAS 0510

Abstract: as4c14400-60jc AS4C14400-40JC alliance as4C14405 AS4C14405-50JC AS4C14405-60JC AS4C14400 AS4C14405 4C14400-70 alliance promotion
Contextual Info: High Performance 1Mx4 CMOS DRAM AS4C14400 AS4C14405 1M-bit × 4 CMOS DRAM Fast page mode or EDO Preliminary information Features • 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 words × 4 bits • High speed - RAS-only or CAS-before-RAS refresh

HY51V18164B

Contextual Info: H Y 51V 18164BSeries •HYUNDAI 1M X 16-bit CMOS DRAM with Extended Data Out DESCRIPTION The HY51V18164B is the new generation and fast dynamic RAM organized 1,048,576 x 16-bit. The HY51V18164B utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques

Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT _ MC-422000A32BA,422000A32FA 2M -WORD BY 32-BIT DYNAMIC RAM MODULE FAST PAGE MODE Description The MC-422000A32BA /FA series is a 2 097 152 words by 32 bits dynamic RAM module on which 4 pieces of 16M DRAM uPD 4218160 are assembled.

HM401

Abstract: BSC MML command
Contextual Info: .uv ii y n Ai HY51V17400A Series 4M x 4-bit CMOS DRAM PRELIMINARY DESCRIPTION The HY51V17400Ais the new generation and fast dynamic RAM organized 4,194,304 x 4-bit. The HY51V17400A utilizes Hyundai's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide

28-pin SOJ SRAM

Abstract: 32K8 AS7C3256-12JC AS7C3256L ci 741 AS7C3256-20JC AS7C3256 AS7C3256-10JC AS7C3256-10PC
Contextual Info: High Performance 32Kx8 3.3V CMOS SRAM AS7C3256 AS7C3256L Low voltage 32K×8 CMOS SRAM Features • Organization: 32,768 words × 8 bits • Single 3.3 ± 0.3V power supply • 5V tolerant I/O specification • High speed - 10/12/15/20 ns address access time

TAA 621

Abstract: MD 202 TAA 621 applications AS7C1026-15JC AS7C1026 AS7C31026 7C1026 AS7C31026-25JC AS7C1026-25JC J-Squared Technologies
Contextual Info: High Performance 64Kx16 CMOS SRAM AS7C1026 AS7C31026 64K×16 CMOS SRAM Preliminary information Features • Organization: 65,536 words × 16 bits • High speed - 12/15/20/25 ns address access time - 6/8/10/12 ns output enable access time • Low power consumption

SIT8103AC-13-33E-24.00000T

Contextual Info: DATA SHEET NEC / / MOS INTEGRATED CIRCUIT _ I1PD42S1780QL, 42178QQL 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE Description The jUPD42S17800L, 4217800L are 2,097,152 w ords by 8 bits CMOS dynamic RAMs. The fast page mode

TAA 621 applications

Abstract: TAA 521 A taa 621 63RD MD 202 Concord Electronics SW 3395 6V TAA 761 A AS7C3513 AS7C513
Contextual Info: High Performance 32Kx16 CMOS SRAM AS7C513 AS7C3513 32K×16 CMOS SRAM Advance information Features • Organization: 32,768 words × 16 bits • High speed - 12/15/20 ns address access time - 6/8/10 ns output enable access time • Low power consumption

Contextual Info: DEVICE OPERATIONS CMOS SDRAM SDRAM Device Operations * Samsung Electronics reserves the right to change products or specification without notice. ELECTRONICS DEVICE OPERATIONS CMOS SDRAM A. MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS

AS7C3512-15PC

Abstract: AS7C3512-25PC AS7C3512-12JC AS7C3512-12PC alliance promotion 60465
Contextual Info: High Performance 64Kx8 3.3V CMOS SRAM AS7C3512 AS7C3512L Low voltage 64K×8 CMOS SRAM Preliminary information Features • Organization: 65,536 words × 8 bits • Single 3.3 ±0.3V power supply • 5V tolerant I/O specification • High speed - 12/15/20/25/35 ns address access time

GH17L

Abstract: cx171 GM71C17403B gm71c18163b 8011S GM71C17403 7011s gm71c18163
Contextual Info: GM7lCl6403B/BL LG Semicon Co.,Ltd. 4,194,304 WORDS x 4 BIT CbIOS DYNAMIC RAM Features Description The GM71 C 16403BIBL is the new generation d y n a m i c R A M organized 4,194,304 words x 4 b i t . GM71 C 16403B/BL h a s realized h i g h e r density, higher performance and various functions

QDD1

Contextual Info: TIMING DIAGRAM II CMOS SDRAM Single Bit Read - Write - Read Cycle Same Page @CAS Latency=3, Burst Length=1 Power Up Sequence Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK

RE300

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /fPD42S17800L, 4217800L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE Description The/iPD42S17800L, 4217800L are 2,097,152 words by 8 bits CMOS dynamic RAMs. The fast page mode _ _ capability realize high speed access and low pow er consumption.

AS7C512-20JC

Abstract: AS7C512 AS7C512-15pc transistor sb 772 AS7C512-12JC AS7C512L-20JC ES 95 SB Plastic 32-pin 300 mil SOIC 7C256 AS7C512-12PC
Contextual Info: High Performance 64Kx8 CMOS SRAM AS7C512 AS7C512L 64K×8 CMOS SRAM Features • Organization: 65,536 words × 8 bits • High speed - 12/15/20/25/35 ns address access time - 3/4/5/6/8 ns output enable access time • Low power consumption - Active: 688 mW max 12 ns cycle

AS7C1024

Abstract: AL205 AS7C31024 IN317
Contextual Info: Hi gh Per for m an ce 128K 128 K x8 C M OS S R A M A S 7C1024 A S 7C31024 1288K ×8 CMOS S R A M 12 Features • Organization: 131,072 words × 8 bits • High speed - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time • Low power consumption

taa 723

Abstract: concord
Contextual Info: High Performance 32Kx9 CMOS SRAM AS7C259 AS7C259L 32K×9 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words × 9 bits • 2.0V data retention (L version) • High speed • Equal access and cycle times – 12/15/20/25/35 ns address access time