TQFP 256 Search Results

cxd 158

Abstract: ot 239 IC51-128 OT 306 IC51-2564-1668-6 IC51-0444-467 IC51-1764 socket Yamaichi ic234 IC51-1764-1505-10 IC217-1444-003
Contextual Info: Series Overview *QFP Quad Flat Packages, Gullwing Leads SMT Devices *QFP variations e.g. BQFP. Series IC51 (Clamshell) QFP, PQFP, TQFP and MQUAD 0.4mm to 1.27 Pitch Part Number (Details) Speci cations Insulation Resistance: Dielectric Withstanding Voltage:

7273B

Contextual Info: SSRAM AS5SS256K18 256K x 18 SSRAM PIN ASSIGNMENT Top View Synchronous Burst SRAM, Flow-Through 100-pin TQFP SA SA CE\ CE2 NC NC bwB\ BWa\ CE2\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ SA SA FEATURES VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC

Contextual Info: SSRAM AS5SS256K36 256K x 36 SSRAM PIN ASSIGNMENT Top View Flow-Through, Synchronous Burst SRAM 100-pin TQFP (DQ, DQC & DQCR) FEATURES              DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc Vss VDD NC Vss

TWL1102

Contextual Info: TWL1102 VOICE-BAND AUDIO PROCESSOR VBAP SLVS264 – NOVEMBER 1999 D 2.7-V Operation D Two Differential Microphone Inputs, One D D D D Programmable for 15-Bit Linear Data or 8-Bit Companded (µ-Law or A-Law) Data D Available in a 32-Terminal TQFP Package

Contextual Info: IS61SF25618 256K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES ADVANCE INFORMATION APRIL 1999 DESCRIPTION Internal s e lf-tim e d w rite cyc le Individua l B yte W rite C o n tro l and G lo b al W rite C lo c k c o n tro lle d , re g is te re d a d d re ss, d a ta and

IDT71T67602

Abstract: IDT71T67802
Contextual Info: 256K X 36, 512K X 18 2.5V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Advance Information IDT71T67602 IDT71T67802 256K x 36/512K x 18. The IDT71T67602/7802 SRAMs contain write,

Contextual Info: K7N803645B K7N803245B K7N801845B 256Kx36/x32 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36 & 256Kx32 & 512Kx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 18. 2001 Preliminary 0.1 1. Add x32 org part and industrial temperature part

Contextual Info: May 2002 AS7C33256NTD32A AS7C33256NTD36A Š 9 .î 65$0 ZLWK 17'TM 1 Features • Organization: 262,144 words x 32 or 36 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.5/3.8/4/5 ns

Contextual Info: 128Kx36,256Kx 18,3.3V SYNCHRONOUS SRAMS WITH PRELIM INARY 2.5V I/O, FLOW-THROUGH OUTPUTS, IDT71V2577 BURST COUNTER, ¡0 7 7 1 V2579 SINGLE CYCLE DESELECT Description Features The IDT71V2577/79 are high-speed SRAMs organized as * 128K x 3 6 ,256K x 18 memory configurations

72235

Abstract: IDT72245LB 72235LB
Contextual Info: IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18,

Contextual Info: 1 28K x ydt Integrated De\/ice Technology, Inc. 36, 256K x 18, 3.3V SYNCHRONOUS SRAMS WITH 2.5V I/O OPTION, PIPELINED OUTPUTS, BURST COUNTER, SINGLE CYCLE DESELECT PRELIMINARY IDT71V2576 IDT71V2578 IDT71V3576 IDT71V3578 FEATURES: DESCRIPTION: • 128K x 36, 256K x 18 memory configurations

l9938

Abstract: K9950 h9940 l9923 L9939 l9940 z9936 z9939 l9934 PQFP208 drawing
Contextual Info: INTEGRATED DEVICE TECHNOLOGY, INC. QUALITY & RELIABILITY MONITORS October 2000 2975 Stender Way, Santa Clara, CA 95054 TEL: 800 345-7015 FAX: (408) 492-8674 QUALITY & RELIABILITY MONITOR REPORT October 2000 TABLE OF CONTENTS Section I: Introduction Section II:

Contextual Info: Æ SW SS K 128K X 36, 256KX 18, 3.3V SYNCHRONOUS SRAMS WITH ZBT FEATURE, BURST COUNTER AND FLOW-THROUGH OUTPUTS PRELIMINARY IDT71 V2557,IDT71 V2559 IDT71V3557, IDT71V3559 FEATURES: • 128K x 36,256K x 18 memory configurations. • Supports high performance system speed -100 MHz

Contextual Info: PRELIMINARY IDT71V3557 IDT71V3559 128K x 3 6 , 256K x 18, 3.3V SYNCHRONOUS SRAMS W ITH ZBT FEATURE, 3.3V I/O, BURST COUNTER, AND FLOW -THROUGH OUTPUTS FEATURES: The IDT71V3557/59 contain address, data-in and control signal registers. The outputs are flow-through no output data register . Output

Contextual Info: PRELIMINARY IDT71V2557 IDT71V2559 128K x 36, 256K x 18, 3.3V SYNCHRONOUS SRAMS W ITH ZBT FEATURE, 2.5V I/O, BURST COUNTER AND FLOW -THROUGH OUTPUTS FEATURES: T h e ID T71V 2557/59 contain address, data-in and control signal registers. The outputs are flow -through no output data register . O utput

Contextual Info: XRT83L38 PRELIMINARY OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR OCTOBER 2003 REV. P1.3.6 GENERAL DESCRIPTION The XRT83L38 is a fully integrated Octal eight channel long-haul and short-haul line interface unit for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or

Samsung EOL

Abstract: IS42S81600F is42s16320 IS43DR16320 IS42S32200L IS49NLC36800 IS43R32400E IS46R Mobile SDRAM IS42S32200E
Contextual Info: Industrial Grade Memory Products Selecting the Right ISSI Industrial Grade Memory Fastest Random Access Access <20ns 288-576Mb Memory No DRC* Lower cost/bit 18-72Mb RLDRAM 10-20ns Easy Interface, Low Power Higher Density Ultra Low Power Synch SRAM <5ns Asynch SRAM

aeha

Abstract: MSC1212Y2
Contextual Info: MSC1211, MSC1212 MSC1213, MSC1214 SBAS323E − JUNE 2004 − REVISED FEBRUARY 2006 Precision AnalogĆtoĆDigital Converter ADC and DigitalĆtoĆAnalog Converters (DACs) with 8051 Microcontroller and Flash Memory FEATURES ANALOG FEATURES D 24 Bits No Missing Codes

XRD98L61AIV-F

Abstract: cctv schematic
Contextual Info: XRD98L61 CCD Image Digitizers with CDS, PGA and 12-Bit A/D May 2001-2 FEATURES • 12-Bit Resolution ADC • 20MHz Sampling Rate • 10-Bit Programmable Gain: 0dB to 36dB PGA • Digitally Controlled Offset-Calibration with Pixel Averager and Hot Pixel Clipper

Contextual Info: |dy Integrated D ev jce Technology, lie . CMOS Triple Bus SyncFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1 , 02 4 x3 6 x 2 PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: There are two errata notices at the end of this data sheet. The corrections have already been incorporated

Contextual Info: XR68C92/192 DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER August 2003 DESCRIPTION The XR68C92/192 is a Dual Universal Asynchronous Receiver and Transmitter with 8 XR68C92 / 16 (XR68C192) bytes transmit and receive FIFO. The XR68C92/192 is a pin-to-pin compatible and an improved version of the

ld1414

Contextual Info: Nomenclature Guide X Types System Management Products SMP X 5 32 3 S8 I Z- 4.5A T1 TAPE AND REEL T1: Tape and Reel T2: Dry Pack PREFIX All Xicor Products INTERFACE 4: 2-Wire Interface 5: SPI Interface PB-FREE OPTION Z: Pb-Free Product ZA: Pb-Free with Anneal

8251a usart interface from z80

Abstract: UDL TM 500 f922 verilog code for 8254 timer l912 256x32 POWER MODULE TM 31 udl 500 78K3 F5S4
Contextual Info: L4E75BS DÜHBÖGb 3ÔÔ B I N E C E CB-C7, 5-VOLT 0.8-M ICRON CELL-BASED CMOS ASIC NEC NEC Electronics Inc. August 1993 Description Figure 1. Integrated HDD Solution with CBC7 Cell-Based ASIC with Embedded 78K3 MPU, Compiled SRAMs and A/D Converters CB-C7 cell-based product family is a 0.8-micron drawn

avr 328

Abstract: 2490F M103C
Contextual Info: Features • High-performance, Low-power AVR 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers