TN5C Search Results

Contextual Info: TN2524 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

Contextual Info: TN2524 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

Contextual Info: TN2524 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling

ADV9502

Abstract: ep320Ipc TNPLD610 N85C220 D5AC312 EP320IDC npld610 EP320IPI EPX780LC84 N5C180
Contextual Info: April 4, 1995 Dear Customer: Effective July 1, 1995, Altera will transition from a dual mark, to a single mark for all products acquired from Intel. In addition, Altera will be converting solely to Altera ordering codes for these products See Table 1 . This change is cosmetic in nature and does not effect

Multiplexers

Abstract: 5C060 5C060-55 EP600 programming 5C060-45 EP600 P5C060-55 intel PLD
Contextual Info: in t e i. 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 8 P-Terms, Selectable SOP Invert, Clear and OE P-Terms for Each Macrocell ■ 16 Macrocells with Programmable I/O

Contextual Info: TN2524 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

N5C090-50

Abstract: 24-MACROCELL d5c090-50 P5C090-50 intel 5C090 SE090 5C090 5C090-60 EP900 D5C090-60
Contextual Info: in t e l» 5C090 24-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ Programmable Clock System with 2 Synchronous Clocks and Asynch­ ronous Clocking Option on all Registers

EP1800

Abstract: N5C180-90 48-MACROCELL 5C180 74HC N5C180 N5C180-70 N5C180-75 TN5C180-75 DL056
Contextual Info: in t e i 5C180 48-MACROCELL CMOS PLD High-Performance LSI Semicustom Logic Alternative for TTL and 74HC SSI and MSI Logic Programmable Registers. Can Be Configured as D, T, SR or JK Types with Individual Reset Controls Low Power; 100 ju,W Typical Standby Dissipation

EP1800

Abstract: N5C180-75 N5C180-70 N5C180-90 48-MACROCELL 5C180 74HC N5C180 TN5C180-75 Tic 4148
Contextual Info: in t e i 5C180 48-MACROCELL CMOS PLD High-Performance LSI Semicustom Logic Alternative for TTL and 74HC SSI and MSI Logic Programmable Registers. Can Be Configured as D, T, SR or JK Types with Individual Reset Controls Low Power; 100 ju,W Typical Standby Dissipation

EP600

Abstract: 5c060 P5C060-55 intel PLD EP600 programming D5C060-45
Contextual Info: in t e i 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 16 Macrocells with Programmable I/O Architecture; up to 20 Inputs 4 Dedicated, 16 I/O or 16 Outputs ■ Programmable Output Registers can be

EP1800 LOGIC DIAGRAM

Abstract: N5C180-90
Contextual Info: in tg l 5C180 48-MACROCELL CMOS PLD • High-Performance LSI Semicustom Logic Alternative for TTL and 74HC SSI and MSI Logic ■ Programmable Registers. Can Be Configured as D, T, SR or JK Types with Individual Reset Controls ■ 48 Macrocells with Programmable I/O

tn5cw

Abstract: TN2524 TN5C fet sot-89 marking code mos die TN2524N8-G TN2524ND
Contextual Info: TN2524 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

tn5cw

Contextual Info: TN2524 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

EP600

Abstract: EP600 eprom 5c060 P5C060-45 EP600 programming 5C060-55 5C06055 EP6003 16-MACROCELL 74HC
Contextual Info: intJ. 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 8 P-Terms, Selectable SOP Invert, Clear and OE P-Terms for Each Macrocell ■ 16 Macrocells with Programmable I/O

N5C180-75

Abstract: EP1800 N5C180 N5C180-90 d2901 5C180 48-MACROCELL 74HC N5C180-70 TN5C180-75
Contextual Info: i n t e i 5 C 1 8 48-MACROCELL CMOS PLD • High-Performance LSI Semicustom Logic Alternative for TTL and 74HC SSI and MSI Logic ■ Programmable Registers. Can Be Configured as D, T, SR or JK Types with Individual Reset Controls ■ 48 Macrocells with Programmable I/O

Contextual Info: Supertex inc. TN2524 N-Channel Enhancement-Mode Vertical DMOS FET Features ►► ►► ►► ►► ►► ►► ►► General Description Low threshold 2.0V max. High input impedance Low input capacitance (125pF max.) Fast switching speeds Low on-resistance

D5C090-50

Abstract: 5C090 p5c09050 SSI 09L P5C090-50
Contextual Info: intpl 5C090 24-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ Programmable Clock System with 2 Synchronous Clocks and Asynch­ ronous Clocking Option on all Registers ■ 24 Macrocells with Programmable I/O

tn5cw

Abstract: tn5c FET SOT-89 FET SOT-89 N-Channel fet sot-89 marking code fet sot-89 product marking TN2524 TN2524N8-G TN2524ND MARKING CODE BV sot-89
Contextual Info: TN2524 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

tn5c

Abstract: marking Tn5C TN5C SOT89 TN2524 TN2524N8 TN2524ND TN25
Contextual Info: TN2524 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package BVDSS / BVDGS RDS ON (max) VGS(th) (max) ID(ON) (min) TO-243AA* Die† 240V 6.0Ω 2.0V 1.0A TN2524N8 TN2524ND * Same as SOT-89. Product supplied on 2000 piece carrier tape reels.