240800 Search Results

80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Contextual Info: SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  Two Instructions Clock Sustained Execution  Four 59 Mbytes s DMA Channels with Data Chaining  Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions clock Execution

80960SA

Abstract: 80960SB 65A176 AD427
Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded ■ Pin Compatible with 80960SB Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache

Contextual Info: P W iy iM D K M W in tJ . 87C51/80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C51/80C51BH/80C51BHP/80C31BH "See Table 1 for Proliferation Options High Performance CHMOS EPROM 5 Interrupt Sources 24 MHz Operation Programmable Serial Port

Contextual Info: inU 8XC196KT COMMERCIAL CHMOS MICROCONTROLLER • High Performance CHMOS 16-Bit CPU ■ Oscillator Fail Detection Circuitry ■ Up to 32 Kbytes of On-Chip EPROM ■ Up to 1 Kbyte of On-Chip Register RAM ■ High Speed Peripheral Transaction Server PTS ■ Up to 512 Bytes of Additional RAM

Contextual Info: « L O G » « ? in te i 8 0 C 19 8 /8 3 C 19 8 /8 0 C 19 4 /8 3 C 1 9 4 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 83C198 — 8 Kbytes of Factory Mask-Programmed ROM 80C198 — ROMIess • ■ ■ ■ ■ ■ ■ ■ ■ 232 Byte Register File Register-to-Register Architecture

Contextual Info: ¡n tg l. 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

Contextual Info: in te i 8XC196KD/8XC196KD20 COMMERCIAL CHMOS MICROCONTROLLER 87C196KD—32 Kbytes of On-Chip OTPROM • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 16 MHz and 20 MHz Available 1000 Byte Register RAM Register-to-Register Architecture 28 Interrupt Sources/16 Vectors

Contextual Info: 80960JS/JC 3.3 V Microprocessor Advance Information Datasheet Product Features • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 80960JS lx the Bus Clock

Contextual Info: in tj, 8XC196KC/8XC196KC20 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 87C196KC—16 Kbytes of On-Chip OTPROM 83C196KC—16 Kbytes ROM 80C196KC—ROMIess • 16 and 20 MHz Available ■ Dynamically Configurable 8-Bit or 16-Bit Buswidth ■ 488 Byte Register RAM

Contextual Info: irrte1 87C51FC/83C51 FC CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 32 KBYTES INTERNAL PROGRAM MEMORY 87C51FC/83C51 FC—3.5 MHz to 12 MHz, VCc = 5V ±20% 87C51FC-1/*3C51 FC-1—3.5 MHz to 16 MHz, Vcc = 5V ±20% 87C51FC-L/83C51FC-L—3.5 MHz to 8 MHz, Vcc = 3.3V ±0.3V

Contextual Info: P fâ H IL O G M A K n f in te i 8 0 C 19 8 /8 3 C 19 8 /8 0 C 19 4 /8 3 C 1 9 4 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 83C198 — 8 Kbytes of Factory Mask-Programmed ROM 80C198 — ROMIess • 232 Byte Register File ■ Full Duplex Serial Port ■ Register-to-Register Architecture

Contextual Info: INTEL CORP UP/PRPHLS bflE D • MfiBbl7S 16b in t e * 87C51 /80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C 51/80C 51B H /80C 51B H P /80C 31B H *S ee Table 1 fo r Proliferation Options High Perform ance CHMOS EPROM 5 Interrupt Sources

Contextual Info: irrte* P K 1IL O IM IO K 1 Ä K V 8XC196K C /8XC 196KC20 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 87C196KC— 16 Kbytes of On-Chip OTPROM 83C196KC— 16 Kbytes ROM 80C196KC—ROMIess 16 and 20 MHz Available • Dynamically Configurable 8-Bit or 488 Byte Register RAM

est 7502 b data sheet

Contextual Info: P E H I1 0 IM 1 D B M IV i n Dt t e : s. i 991 82495XP CACHE CONTROLLER/ 82490XP CACHE RAM • Two-Way, Set Associative, Secondary Cache for i860 XP Microprocessor MESI Cache Consistency Protocol ■ 50 MHz “No Glue” Interface with CPU Maintains Consistency with Primary

Contextual Info: in te l M80C51FB CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER MiHtary M80C51FB — 3.5 MHz to 12 MHz, VCc = 5V ± 10% M80C51FB-16 — 3.5 MHz to 16 MHz, Vcc = 5V ± 10% High Performance CHMOS EPROM 32 Programmable I/O Lines Three 16-Bit Timer/Counters 7 Interrupt Sources

Contextual Info: 87C196LA-20 MHz CHMOS 16-bit Microcontroller Automotive Advanced Inform ation D atasheet Product Features • Up to 20 M Hz operation ■ 24 Kbytes o f on-chip OTPROM ■ Enhanced full-duplex, synchronous serial I/O port SSIO ■ 768 bytes o f on-chip register RAM

Contextual Info: [PIM2>[E U T P^E^OO in te i 80960HA/HD/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Binary Compatible with Other80960 Processors • Two Instructions/Clock Sustained Execution 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers

Contextual Info: 80C196EA - Commercial in t e l 1,0 Product Overview The 80C196EA are typically used for high speed event control systems. Commercial applications include modem, motor-control systems, printers, photocopiers, air-conditioner control systems, disk drives and m edical instruments. It is especially w ell suited to applications that benefit from its

Contextual Info: A B W A N O B O N IP O R Q W O Q N in te i 82091AA ADVANCED INTEGRATED PERIPHERAL AIP • Single-Chip PC Compatible I/O Solution for Notebook and Desktop Platforms: — 82078 Floppy Disk Controller Core — Two 16550 Compatible UARTs — One Multi-Function Parallel Port

Contextual Info: in te i, 83C51 KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER Direct Drive LED Outputs — Four Pins P3.7:4 — 13 mA Typical Current Sink Capability 20 pF Cap On-chip for RC Resonator — Frequency Selectable (4-6 MHz) • 128-byte On-chip RAM Memory ■ Clock/Data Drivers to Motherboard

Contextual Info: 87C196CA/87C196CB 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0 Automotive m High Performance CHMOS 16-Bit CPU • Full Duplex Synchronous Serial I/O Port SSIO (up to 20 MHz Operation) ■ Register-Register Architecture ■ Up to 56 Kbytes of On-Chip EPROM

132-Lead

Abstract: AD30/ako 451 960
Contextual Info: A E W Â N l ! DKIIF ß}[ü iflA 70® ß !0 in te l 80960J A /JF EMBEDDED 32-BIT MICROPROCESSOR High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers

Contextual Info: intei IP H g y M O IM D f t f 8XC196KB/8XC196KB16 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 8 Kbytes of On-Chip ROM/OTP Available Dynamically Configurable 8-Bit or 16-Bit Buswidth 232 Byte Register File Full Duplex Serial Port Register-to-Register Architecture

Contextual Info: INTEL CORP UP/PR PHL S 44E D E3 4ö2bl7S 0104S11 2 E3ITL1 [P G & flG Ä » 87C196KB/87C198KB16 HIGH PERFORMANCE CHMOS MICROCONTROLLER 8 Kbytes of On-Chip EPROM 232 Byte Register File Dynamically Configurable 8-Blt or 16-Bit Buswidth Register-to-Register Architecture