TIM CS Search Results

Trimble lassen

Abstract: Conexant GPS Jupiter TCJ-ST-0-000-0 Trimble sk8 U-blox TIM-CJ navman gps board TIM TCJ-ST-0-000-0 sbr-ls GSP2E sirf grf2i
Contextual Info: u-blox: Products -> Receiver Boards -> TIM-CJ, TIM-CL, TIM-CS Search Register Home Company Contacts Distributors Products Chipsets Macro Components Receiver Boards SBR-LS GPS-PS2 TIM-CJ, TIM-CL, TIM-CS Documents Tools Firmware FAQ Smart Antennas Accessories

U-blox TIM-CJ

Abstract: Conexant GPS Jupiter sirf grf2i GSP2E Trimble sk8 GPS Antenna lassen ic datasheet 7447 TCJ-ST-0-000-0 TIM CS TTL 7447
Contextual Info: TIM-CJ, TIM-CL, TIM-CS GPS Receiver Board SiRFstar II Positioning Engine The TIM-CJ, TIM-CL and TIM-CS are fully selfcontained OEM GPS receiver boards powered by TIM which are based on the SiRFstar™ II GPS technology. These boards are available in different form factors, comparable to those of

U-blox TIM-CJ

Abstract: Trimble sk8 TCJ-ST-0-000-0 Trimble lassen navman Conexant GPS Jupiter u-blox 6 GPS receivers U-blox AG sirf grf2i TIM-CJ
Contextual Info: TIM-CJ, TIM-CL, TIM-CS GPS Receiver Board SiRFstar II Positioning Engine The TIM-CJ, TIM-CL and TIM-CS are fully selfcontained OEM GPS receiver boards powered by TIM which are based on the SiRFstar™ II GPS technology. These boards are available in different form factors, comparable to those of

digital stopwatch

Abstract: 6-Digit Electronic Stopwatch LITRONIX dl DF213 LITRONIX DF213CJ 18 pin led display ic three digit STOPWATCH 8 DIGIT Beckman Industrial BECKMAN
Contextual Info: designed fo r . • • B E N E F IT S T w o Tim ing Fu n ction s in O ne 1C • Sports Tim ing Auto Racing, Track, Sw im m ing, Rodeo, Sailing , Football, Soccer ■ Industrial Tim ing ^ Testing, Time-Motion Studies, Process Tim ing ■ Scientific Tim ing

HYB51

Contextual Info: SIEM ENS HYB 511002-10/-12 1 048 576 Bit Static Column Dynamic RAM 1 048 576 w o rd s by 1 b it o rg a n iz a tio n Fast access and c ycle tim e 100 ns access tim e 190 ns c ycle tim e HYB 511002-10 120 ns access tim e 220 ns c ycle tim e (HYB 511002-12)

Contextual Info: IBM0165800B 8M x 8 12/11 DRAM Features • 8,388,608 word by 8 bit organization • Performance: -50 -60 jtRAC ! RAS Access Tim e 50ns 60ns jtcAC ! CAS Access Tim e 13ns ' 5ns ;1aa ! Column Address Access Tim e I 25ns 30ns |1rc I Cycle Tim e 90ns ! 11 0 ns i

CERAMIC LEADLESS CHIP CARRIER LCC 44

Abstract: atmel at28C010 AT28C010 5962-38267
Contextual Info: Features * Fast Read Access Tim e -1 2 0 ns * Autom atic Page W rite Operation Internal Address and Data Latches for 128-Bytes Internal Control Tim er * Fast W rite Cycle Tim e Page W rite Cycle Tim e -1 0 ms Maximum 1 to 128-Byte Page W rite Operation * Low Power Dissipation

41257

Abstract: H R C M F 2J 225
Contextual Info: SIEMENS HYB 41257-12/-15/-20 262,144-Bit Dynamic Random Access Memory RAM • Fast nibble m ode on read and w rite cycles via addresses A8 row and A8 colum n 30 ns access tim e 65 ns cycle tim e (HYB 41257-12) 40 ns access tim e 80 ns cycle tim e (HYB 41257-15)

0a0c1

Contextual Info: Features * Single Voltage Operation - 5V Read - 5V Reprogramming * Fast Read Access Tim e - 90 ns * Internal Program Control and Tim er * 8K Bytes Boot Block With Lockout * Fast Erase Cycle Tim e - 1 0 seconds * Byte-By-Byte Programming - 50 ps/Byte * Hardware Data Protection

Contextual Info: Product Brief August 1998 group Lucent Technologies Bell Labs Innovations T TS I1K 16T 1024-C hannel, 16-H ighw ay Tim e-Slot Interchanger Features Sixteen full-duplex, serial tim e-division m ultiplexed TDM highw ays. Full availability, nonblocking 1024-channel tim e /

Contextual Info: Product Brief August 1998 group Lucent Technologies Bell Labs Innovations T TS I4K 32T 4096-C hannel, 32-H ighw ay Tim e-Slot Interchanger Features T hirty-tw o full-duplex, serial tim e-division m ulti­ plexed TDM highw ays. Full availability, nonblocking 4096-channel tim e /

KM428C128

Abstract: 428C128 256X8 CMOS RAM 428-C KM428C128-6
Contextual Info: r PRELIMINARY v KM428C128 CMOS VIDEO RAM 1 28K X 8 Bit CMOS Video RAM FEATURES • Dual port Architecture 128K x 8 bits RAM port 256 x 8 bits SAM port • Performance - Speed Parameter RAM access tim e tRAc RAM access tim e (tcAc) RAM cycle tim e (tRc)

Contextual Info: MOSEL VI TEL IC PRELIMINARY V53C516400A 4M x 4 FAST PAGE MODE CMOS DYNAMIC RAM V53C516400A 50 60 Max. R A S Access Tim e, Ì raq 50 ns 60 ns Max. Colum n Address Access Tim e, (Ì q aa ) 2 5 ns 30 ns Min. P age M ode C ycle Tim e, (tpc) 3 5 ns 4 0 ns Min. R ead /W rite C ycle Tim e, (tRC)

Contextual Info: Product Brief August 1998 group Lucent Technologies Bell Labs Innovations T TS I2K 32T 2048-C hannel, 32-H ighw ay Tim e-Slot Interchanger Features T hirty-tw o full-duplex, serial tim e-division m ulti­ plexed TDM highw ays. Full availability, nonblocking 2048-channel tim e /

658128

Contextual Info: KM658128/L/L-L/LD/LD-L Pseudo SRAM 128K X 8 Bit CMOS Pseudo Static RAM GENERAL DESCRIPTION FEATURES • Fast Access Time: — CE A ccess Tim e . 80,100,120ns Max. — Cycle Tim e . Random R ead/W rite Cycle Tim e . 130,160,190ns (Max.) • Low Power Dissipation . 200m W typ. (Active)

Contextual Info: IBM0165405B IBM0165405P 16M x 4 12/12 EDO DRAM Features • 16,777,216 word by 4 bit organization Read-Mod ify-Write • Single 3.3 ± 0.3V power supply Performance: -50 -60 I rac RAS Access Tim e 50 ns 60ns tcAC GAS Access Tim e 13ns 15ns •*AA ; Colum n Address Access Tim e

faa11

Abstract: 5118165 d lt 7210
Contextual Info: SIEMENS 1M X 32-Bit Dynamic RAM Module Hyper Page Mode - EDO Version HYM 321005S/GS-50/-60 Advanced Inform ation • 1 048 576 w ords by 32-bit organization • Fast access and cycle tim e 50 ns access time 84 ns cycle tim e (-50 version) 60 ns access tim e

6s3b

Abstract: Q67100-Q2098 Q67100-Q2099
Contextual Info: SIEM EN S 8M X 32-Bit EDO-DRAM Module HYM328025S/GS-50/-60 Advanced Inform ation • 8 388 608 words by 32-bit organization • Fast access and cycle tim e 50 ns access time 84 ns cycle tim e -50 version 60 ns access time 104 ns cycle tim e (-60 version)

Contextual Info: TEXAS INSTR -CASIC/MEMORY} Ì7 Ô Ë | flìtlTES D074Ô31 □ 262,144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY FEBRUARY 1988 262,144 x 4 Organization JD PACKAGE TOP VIEW Performance Ranges: AC C ESS AC C ESS AC C ESS TIM E TIM E TIM E • e 4 5 ns *a(CA)

Contextual Info: IBM11 D4475B IBM11 E4475B IBM11D8475B IBM11E8475B 4M/8M x 32 Desktop ECC-on-SIMM Features • 72-Pin JEDEC Standard Single-In-Line Memory Module • Performance: : -6R : I rac RAS Access Tim e ; 60ns : tc A C CAS Access Tim e : 18ns : U a I rc t|HPC A ccess Tim e From Address ; 30ns ;

AA S50

Contextual Info: SIEM EN S 4M x 32-Bit Dynamic RAM Module HYM 324020S/GS-50/-60 Advanced Information • 4 194 304 words by 32-bit organization alternative 8 388 608 words by 16-bit • Fast access and cycle tim e 50 ns access time 90 ns cycle tim e (-50 version) 60 ns access tim e

71054-10

Abstract: PD71054 uPD70208 MPD70216 V30TM 71054 JUPD71054C uPD71054 mpd70116 D71054
Contextual Info: MOS INTEGRATED CIRCUIT ¿¿PD710 5 4 PRO G RAM M ABLE TIM E R /C O U N TE R The ¿iPD71054 is a high-performance programmable tim er/counter designed fo r tim ing control applications in m icrocom puter systems. The jitPD71054 is fabricated by CMOS technology in order to realize low power consump­

Contextual Info: MOSEL VITELIC V54C365804VA HIGH PERFORMANCE 3.3 VOLT8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2M bit X 8 PRELIMINARY 8 10 System Frequency fCK 125 MHz 100 MHz Clock Cycle Tim e (tcK 3) 8 ns 10 ns Clock Access Tim e (tAC3) CAS Latency = 3 7 ns 8 ns Clock Access Tim e (tAC2) CAS Latency = 2

Contextual Info: SIEMENS 4M x 36-Bit Dynamic RAM Module HYM 364020S/GS-60/-70 Advanced Inform ation • 4 194 304 words by 36-Bit organization alternative 8 388 608 w ords by 18-bit • Fast access and cycle tim e 60 ns access time 110 ns cycle tim e (-60 version) 70 ns access tim e