TEXAS INSTRUMENTS DSP DESIGN AUTOMOTIVE 1992 Search Results

SN74F1018

Contextual Info: SN74F1018 18-BIT SCHOTTKY BARRIER DIODE R-C BUS-TERMINATION ARRAY SDFS094 – NOVEMBER 1992 – REVISED DECEMBER 1993 • • • DW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current . . . 300 mA 18-Bit Array Structure Suited for

Contextual Info: REG1117 REG1117A SBVS001D − OCTOBER 1992 − REVISED JULY 2004 800mA and 1A Low Dropout Positive Regulator 1.8V, 2.5V, 2.85, 3.3V, 5V, and Adjustable FEATURES D FIXED AND ADJUSTABLE VERSIONS D 2.85V MODEL FOR SCSI-2 ACTIVE D D D D D D TERMINATION OUTPUT CURRENT:

5G4 MARKING

Contextual Info: REG1117 REG1117A SBVS001D − OCTOBER 1992 − REVISED JULY 2004 800mA and 1A Low Dropout Positive Regulator 1.8V, 2.5V, 2.85, 3.3V, 5V, and Adjustable FEATURES D FIXED AND ADJUSTABLE VERSIONS D 2.85V MODEL FOR SCSI-2 ACTIVE D D D D D D TERMINATION OUTPUT CURRENT:

bb11175

Abstract: bb11174 bb1117 r111718 bb1117a bb11172 R111725 BB1117F4 REG1117 REG1117-2
Contextual Info: REG1117 REG1117A SBVS001D − OCTOBER 1992 − REVISED JULY 2004 800mA and 1A Low Dropout Positive Regulator 1.8V, 2.5V, 2.85, 3.3V, 5V, and Adjustable FEATURES D FIXED AND ADJUSTABLE VERSIONS D 2.85V MODEL FOR SCSI-2 ACTIVE D D D D D D TERMINATION OUTPUT CURRENT:

ti marking

Abstract: bb11172 bb11175 bb11174 BB1117F4 REG1117 REG1117-2 REG1117-3 REG1117-5 REG1117A
Contextual Info: REG1117 REG1117A SBVS001D − OCTOBER 1992 − REVISED JULY 2004 800mA and 1A Low Dropout Positive Regulator 1.8V, 2.5V, 2.85, 3.3V, 5V, and Adjustable FEATURES D FIXED AND ADJUSTABLE VERSIONS D 2.85V MODEL FOR SCSI-2 ACTIVE D D D D D D TERMINATION OUTPUT CURRENT:

SNJ557202E

Contextual Info: SNJ557202E 160ĆCHANNEL LCD DRIVER FOR DOT MATRIX STN SGLS044 − JANUARY 1992 • • • • • • • • • One Chip for Both Common Row and Segment (Column) Driving Duty Cycle for LCD Driver Is Over 1/400 Recommended VEE Voltage Range for LCD Driver: 20 V to 42 V (45 V Max)

74ACT11132

Abstract: SCAS177
Contextual Info: 74ACT11132 QUADRUPLE POSITIVEĆNAND GATE WITH SCHMITTĆTRIGGER INPUTS ą SCAS177 − D3974, JANUARY 1992 − REVISED APRIL 1993 • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise

Contextual Info: 74ACT11132 QUADRUPLE POSITIVEĆNAND GATE WITH SCHMITTĆTRIGGER INPUTS ą SCAS177 − D3974, JANUARY 1992 − REVISED APRIL 1993 • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise

74ACT16864

Abstract: 54ACT16864
Contextual Info: 54ACT16864, 74ACT16864 18ĆBIT BUS TRANSCEIVERS WITH 3ĆSTATE OUTPUTS SCAS244A − JUNE 1992 − REVISED APRIL 1996 D Members of the Texas Instruments D D D D D D D 54ACT16864 . . . DW PACKAGE 74ACT16864 . . . DL PACKAGE TOP VIEW Widebus  Family Inputs Are TTL-Voltage Compatible

74ACT16864

Contextual Info: 54ACT16864, 74ACT16864 18ĆBIT BUS TRANSCEIVERS WITH 3ĆSTATE OUTPUTS SCAS244A − JUNE 1992 − REVISED APRIL 1996 D Members of the Texas Instruments D D D D D D D 54ACT16864 . . . DW PACKAGE 74ACT16864 . . . DL PACKAGE TOP VIEW Widebus  Family Inputs Are TTL-Voltage Compatible

Contextual Info: CDC328A 1ĆLINE TO 6ĆLINE CLOCK DRIVER WITH SELECTABLE POLARITY SCAS327B − DECEMBER 1992 − REVISED NOVEMBER 1995 D OR DB PACKAGE TOP VIEW D Low Output Skew for Clock-Distribution D D D D D D D and Clock-Generation Applications TTL-Compatible Inputs and Outputs

Contextual Info: 74ACT11158 QUADRUPLE 2ĆLINE TO 1ĆLINE DATA SELECTOR/MULTIPLEXER ą ą SCAS181 − D3979, JANUARY 1992 − REVISED APRIL 1993 • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout

74ACT11158

Contextual Info: 74ACT11158 QUADRUPLE 2ĆLINE TO 1ĆLINE DATA SELECTOR/MULTIPLEXER ą ą SCAS181 − D3979, JANUARY 1992 − REVISED APRIL 1993 • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout

74AC11800

Contextual Info: 74AC11800 TRIPLE 4ĆINPUT AND/NAND GATES ą ą SCAS233 − AUGUST 1992 − REVISED APRIL 1993 • DW PACKAGE TOP VIEW Suitable for Use in Applications Such as: − Differential Line Drivers − Complementary Input Circuits for Decoders and Code Converters

Contextual Info: 74AC11800 TRIPLE 4ĆINPUT AND/NAND GATES ą ą SCAS233 − AUGUST 1992 − REVISED APRIL 1993 • DW PACKAGE TOP VIEW Suitable for Use in Applications Such as: − Differential Line Drivers − Complementary Input Circuits for Decoders and Code Converters

CDC328A

Contextual Info: CDC328A 1ĆLINE TO 6ĆLINE CLOCK DRIVER WITH SELECTABLE POLARITY SCAS327B − DECEMBER 1992 − REVISED NOVEMBER 1995 D Low Output Skew for Clock-Distribution D D D D D D D D OR DB PACKAGE TOP VIEW and Clock-Generation Applications TTL-Compatible Inputs and Outputs

SN54ABT32245

Abstract: SN74ABT32245 ABT32245
Contextual Info: SN54ABT32245, SN74ABT32245 36ĆBIT BUS TRANSCEIVERS WITH 3ĆSTATE OUTPUTS SCBS228C − JUNE 1992 − APRIL 1995 • • • • • Members of the Texas Instruments Widebus +  Family State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation

SN54ABT16863

Abstract: SN74ABT16863 SN74ABT16863DLR
Contextual Info: SN54ABT16863, SN74ABT16863 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS225C – JUNE 1992 – REVISED MAY 1997 D D D D D D D D D SN54ABT16863 . . . WD PACKAGE SN74ABT16863 . . . DL PACKAGE TOP VIEW Members of the Texas Instruments Widebus  Family

Contextual Info: 54ACT16474, 74ACT16474 18ĆBIT REGISTERED BUS TRANSCEIVERS WITH 3ĆSTATE OUTPUTS SCAS238A − MAY 1992 − REVISED APRIL 1996 54ACT16474 . . . WD PACKAGE 74ACT16474 . . . DL PACKAGE TOP VIEW D Members of the Texas Instruments D D D D D D D Widebus  Family

54ACT16474

Abstract: 74ACT16474
Contextual Info: 54ACT16474, 74ACT16474 18ĆBIT REGISTERED BUS TRANSCEIVERS WITH 3ĆSTATE OUTPUTS SCAS238A − MAY 1992 − REVISED APRIL 1996 D Members of the Texas Instruments D D D D D D D 54ACT16474 . . . WD PACKAGE 74ACT16474 . . . DL PACKAGE TOP VIEW Widebus  Family

texas rfid 1991

Abstract: CDC329
Contextual Info: CDC329 1ĆLINE TO 6ĆLINE CLOCK DRIVER WITH SELECTABLE POLARITY SCBS117A−D4501, JANUARY 1991−REVISED NOVEMBER 1992 • • • • • • • • D PACKAGE TOP VIEW Low Output Skew for Clock-Distribution and Clock-Generation Applications State-of-the-Art EPIC-ΙΙB  BiCMOS Design

Contextual Info: CDC329 1ĆLINE TO 6ĆLINE CLOCK DRIVER WITH SELECTABLE POLARITY SCBS117A−D4501, JANUARY 1991−REVISED NOVEMBER 1992 • • • • • • • • D PACKAGE TOP VIEW Low Output Skew for Clock-Distribution and Clock-Generation Applications State-of-the-Art EPIC-ΙΙB  BiCMOS Design

1A11

Abstract: 1A12 1A13 1A15 1A16 SN54ABT32543 SN74ABT32543 texas instruments DSP design automotive 1992
Contextual Info: SN54ABT32543, SN74ABT32543 36ĆBIT REGISTERED BUS TRANSCEIVERS WITH 3ĆSTATE OUTPUTS ą SCBS230B − JUNE 1992 − REVISED JULY 1994 • • • • • Members of the Texas Instruments Widebus +  Family State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation

15-V

Abstract: EIA-232 LT1039 LT1039CDW LT1039CDWR LT1039CN
Contextual Info: LT1039 TRIPLE EIAĆ232 LINE TRANSCEIVER ą ą SLLS105B − D3627, FEBRUARY 1991 − REVISED JANUARY 1992 • • • • • • • • • Meets All EIA-232-D Revision of RS-232-C Specifications DW OR N PACKAGE (TOP VIEW) Three Independent Drivers and Receivers