TDAT40 Search Results

nrzi to nrz circuit diagram

Abstract: nrzi to nrz converter circuit diagram MXIC MX mxic
Contextual Info: 1 OOBASETX PHYSICAL DATA TRANSCEIVER 1.0 FEATURES • • • • • • • • • • • Full-Duplex Operation Generates 125-Mhz Transmit Clock and 25-Mhz SYMCLK Converts 5-Bit Parallel Transmit Data to 1-Bit Serial Data Converts Transmit NRZ Data to NRZI Data

MX98741

Contextual Info: INDEX MX98741 XRC 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • Eight 100 BASE-TX/FX ports; each port individually configurable to TX or FX • Direct interface with analog clock generation/recovery chips • Three Media Independent Interface MII • Expandable to increase number of repeater ports

T05A

Abstract: MX98741 MX98742 MX98745
Contextual Info: PRELIMINARY MX98745 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • IEEE 802.3u D5 repeater and management compatible • Support 7 TX/FX ports and 1 universal port TX or MII port selectable • Support 8-scale utilization and collision rate LED display

MC68836

Abstract: MX98741 MX98742 MX98745 AM78965
Contextual Info: PRELIMINARY MX98745 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • IEEE 802.3u D5 repeater and management compatible • Support 7 TX/FX ports and 1 universal port TX or MII port selectable • Support 8-scale utilization and collision rate LED display

Contextual Info: FVeliminaiy n Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 • Line state detection ■ ■ Hardware Physical Connection Management (PCM) support

T-75-49

Abstract: AM79865 AMD Supernet 2 AM79866JC MAE 411
Contextual Info: ADV MICRO T E L E C O M MAE D □ 257527 0 0 3 0 ^ 2 □ • AMD3 Preliminary a Advanced Micro Devices Am79865/Am79866 Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS ■ ■ ■ ■ Parallel Input to the PDT Is a 5-bit encoded

nrzi to nrz converter circuit diagram

Abstract: nrzi TDAT40 kd212 XFORMER MX98702 MX98704 MX98704QC MX98713 MX98741
Contextual Info: INDEX PRELIMINARY MX98704 100BASE-TX PHYSICAL DATA TRANSCEIVER 1.0 FEATURES • • • • • • • • • • • Full-Duplex Operation Generates 125-Mhz Transmit Clock and 25-Mhz SYMCLK Converts 5-Bit Parallel Transmit Data to 1-Bit Serial Data Converts Transmit NRZ Data to NRZI Data

AM78965

Abstract: pal16v8 extcrs2
Contextual Info: Ü Ü !Ï • W iJ I U MX98741 1.0 XRC 100 BASE-TX/FX Repeater Controller Features • 208-pin, C M O S device in PQFP package • Eight 100 B A S E -TX /FX ports; each port individually configurable to T X or FX • Direct interface with analog clock generation/recovery chips

Contextual Info: PRELIM INARY MX98705 100 BASE-TX PHY-PMD TRANSCEIVER 1. FEATURES Five Bit TTL Nibble at 25 MHz Input/Output 25 MHz received recovery clock Operates over 100 Meters of STP and Category 5 UTP Cable >7.5 dB Single +5V Supply 52 PQFP package • Complies with IEEE 802.3 Standards

6K8k

Abstract: t41 datasheet 10BASE MX98741 MX98742 SA10 SA11 SA12 SA13 2-port bridge fiber UTP
Contextual Info: INDEX PRELIMINARY MX98742 FEBC 100 BASE FAST ETHERNET BRIDGE CONTROLLER 1.0 FEATURES * * * * * * * * * * * * 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging Minimum 16K byte, maximum 256K byte buffer memory Selectable TX/FX/T4 symbol-level repeater, MII interfaces, and 10BASE serial port

Contextual Info: H Preliminary Advanced Micro Devices Am79865/Am79866 Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS • ■ ■ ■ Parallel Input to the PDT Is a 5-bit encoded NRZ symbol clocked by LSCLK Parallel output from the PDR Is a 5-bit

mlt 22 612

Abstract: nrzi clock recovery mlt resistor MX98705 mlt 44 pin
Contextual Info: PRELIMINARY MX98705 100 BASE-TX PHY-PMD TRANSCEIVER 1. FEATURES • Five Bit TTL Nibble at 25 MHz Input/Output • 25 MHz received recovery clock • Operates over 100 Meters of STP and Category 5 UTP Cable >7.5 dB • Single +5V Supply • 52 PQFP package

6K8k

Abstract: AM79866 broadcom 1024 10BASE MX98741 MX98742 SA10 SA11 SA12 SA13
Contextual Info: PRELIMINARY MX98742 FEBC 100 BASE FAST ETHERNET BRIDGE CONTROLLER 1.0 FEATURES * * * * * * * * * * * * 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging Minimum 16K byte, maximum 256K byte buffer memory Selectable TX/FX/T4 symbol-level repeater, MII interfaces, and 10BASE serial port

jami

Abstract: XRC circuit diagram 128-PIN MX98741 MX98745 MX98746
Contextual Info: PRELIMINARY MX98746 100 BASE-TX/FX 5-PORT CLASSII REPEATER CONTROLLER 1.0 FEATURES • Separate jabber and partition state machines for each port • On-chip elasticity buffer for PHY signal re-timing to the MX98746 clock source • Contents of internal register loaded from EEPROM

Contextual Info: Preliminary Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS • ■ ■ ■ Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 Hardware Physical Connection Management (PCM) support Performs Physical Connection insertion and

Contextual Info: PRELIMINARY MX98746 100 BASE-TX/FX 5-PORT CLASSII REPEATER CONTROLLER 1.0 FEATURES • S eparate ja b b e r and partition state m achines fo re a c h port • O n-chip e la sticity buffer fo r PHY signal re-tim ing to the M X 98746 clo ck source •C o n te n ts of internal register loaded from EEPRO M

128-PIN

Abstract: MX98741 MX98745 MX98746
Contextual Info: INDEX PRELIMINARY MX98746 100 BASE-TX/FX 5-PORT CLASSII REPEATER CONTROLLER 1.0 FEATURES • Separate jabber and partition state machines for each port • On-chip elasticity buffer for PHY signal re-timing to the MX98746 clock source • Contents of internal register loaded from EEPROM

Contextual Info: MXIC _M X 9 8 7 4 2 FEBC 1 OO BASE FAST ETHERNET BRIDGE CONTROLLER 1.0 FEATURES 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging Minimum 16K byte, maximum 256K byte buffer memory Selectable TX/FX/T4 symbol-level repeater, Mil interfaces, and 10BASE serial port

nrzi to nrz converter circuit diagram

Abstract: nrzi to nrz circuit diagram MX98705 Mlt-3
Contextual Info: INDEX PRELIMINARY MX98705 100 BASE-TX PHY-PMD TRANSCEIVER 1. FEATURES • Five Bit TTL Nibble at 25 MHz Input/Output • 25 MHz received recovery clock • Operates over 100 Meters of STP and Category 5 UTP Cable >7.5 dB • Single +5V Supply • 52 PQFP package

crsa 58

Abstract: MX98741
Contextual Info: MX98741 XRC 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • Eight 100 BASE-TX/FX ports; each port individually configurable to TX or FX • Direct interface with analog clock generation/recovery chips • Three Media Independent Interface MII • Expandable to increase number of repeater ports