MX98741 Search Results

MX98741

Contextual Info: INDEX MX98741 XRC 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • Eight 100 BASE-TX/FX ports; each port individually configurable to TX or FX • Direct interface with analog clock generation/recovery chips • Three Media Independent Interface MII • Expandable to increase number of repeater ports

1802 fx

Abstract: MX98741 MDC160 Sk A-3120 TDAT54
Contextual Info: MX98741 K M r B «assss» • » — ■ I XRC 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • Eight 100 BASE-TX/FX ports; each port individually configurable to TX or FX • Direct interface with analog clock generation/recov­ ery chips • Three Media Independent Interface Mil

7474

Abstract: QS6611 SW-SPsT datasheet 7474 MX98741 QS162244FCT TSC25 sw-SPST-2 of 7474 of d sw spst
Contextual Info: A B C +5V D E G H I J HUB A QS162244FCT 9 F 9 QS6611 R1 10K TXD[0.4] X1 28 20 TSC25 U?A 7474 4 2 50 Mhz 3 PR 8 D Q QS6611 5 CL Q X1 8 TXD[0.4] CLK MX98741 X1 28 6 TSC25 20 1 QS6611 TXCLK TXD[0.4] X1 28 7 7 TXCLK 20 Closed to use as Master clock / Open to use as Slave

AM78965

Abstract: pal16v8 extcrs2
Contextual Info: Ü Ü !Ï • W iJ I U MX98741 1.0 XRC 100 BASE-TX/FX Repeater Controller Features • 208-pin, C M O S device in PQFP package • Eight 100 B A S E -TX /FX ports; each port individually configurable to T X or FX • Direct interface with analog clock generation/recovery chips

crsa 58

Abstract: MX98741
Contextual Info: MX98741 XRC 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • Eight 100 BASE-TX/FX ports; each port individually configurable to TX or FX • Direct interface with analog clock generation/recovery chips • Three Media Independent Interface MII • Expandable to increase number of repeater ports

T05A

Abstract: MX98741 MX98742 MX98745
Contextual Info: PRELIMINARY MX98745 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • IEEE 802.3u D5 repeater and management compatible • Support 7 TX/FX ports and 1 universal port TX or MII port selectable • Support 8-scale utilization and collision rate LED display

RTL8201BL

Abstract: DLINK dfe 808tx RTL8204 DFE-808TX LXT9781HC Realtek RTL8201bL DP83223P DLINK Realtek RTL8204 EH5021C
Contextual Info: RTL8201BL HUB/SWITCH Compatibility Test Test environment : 1. One RTL8201BL transmits packets to hub/switch and four RTL8201BL receive packets from hub/switch 2. Tested Cat. 5 Twist-pair cable length 100M. 3. Run about half hour with random data and random packet length

Contextual Info: PRELIMINARY MX98745 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • On-chip elasticity buffer for PHY signal re-timing to the MX98745 clock source • Contents of internal register loaded from EEPROM • PCS/MAC type Mil interface selectable • CMOS device features high integration and low power

MC68836

Abstract: MX98741 MX98742 MX98745 AM78965
Contextual Info: PRELIMINARY MX98745 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • IEEE 802.3u D5 repeater and management compatible • Support 7 TX/FX ports and 1 universal port TX or MII port selectable • Support 8-scale utilization and collision rate LED display

nrzi to nrz converter circuit diagram

Abstract: nrzi TDAT40 kd212 XFORMER MX98702 MX98704 MX98704QC MX98713 MX98741
Contextual Info: INDEX PRELIMINARY MX98704 100BASE-TX PHYSICAL DATA TRANSCEIVER 1.0 FEATURES • • • • • • • • • • • Full-Duplex Operation Generates 125-Mhz Transmit Clock and 25-Mhz SYMCLK Converts 5-Bit Parallel Transmit Data to 1-Bit Serial Data Converts Transmit NRZ Data to NRZI Data

Contextual Info: MX98743 FEM 100 Base Fast Ethernet Management Chip 1.0 FEATURES * Support IEEE 802.3 MIBs * Support RMON etherStatsEnty and etherStats History group * 8/12/32 bit microprocessor interface * Linear mapped registers for easy programming * Embedded MAC for low-cost management functions implementation

6K8k

Abstract: t41 datasheet 10BASE MX98741 MX98742 SA10 SA11 SA12 SA13 2-port bridge fiber UTP
Contextual Info: INDEX PRELIMINARY MX98742 FEBC 100 BASE FAST ETHERNET BRIDGE CONTROLLER 1.0 FEATURES * * * * * * * * * * * * 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging Minimum 16K byte, maximum 256K byte buffer memory Selectable TX/FX/T4 symbol-level repeater, MII interfaces, and 10BASE serial port

6K8k

Abstract: AM79866 broadcom 1024 10BASE MX98741 MX98742 SA10 SA11 SA12 SA13
Contextual Info: PRELIMINARY MX98742 FEBC 100 BASE FAST ETHERNET BRIDGE CONTROLLER 1.0 FEATURES * * * * * * * * * * * * 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging Minimum 16K byte, maximum 256K byte buffer memory Selectable TX/FX/T4 symbol-level repeater, MII interfaces, and 10BASE serial port

jami

Abstract: XRC circuit diagram 128-PIN MX98741 MX98745 MX98746
Contextual Info: PRELIMINARY MX98746 100 BASE-TX/FX 5-PORT CLASSII REPEATER CONTROLLER 1.0 FEATURES • Separate jabber and partition state machines for each port • On-chip elasticity buffer for PHY signal re-timing to the MX98746 clock source • Contents of internal register loaded from EEPROM

128-PIN

Abstract: MX98741 MX98745 MX98746
Contextual Info: INDEX PRELIMINARY MX98746 100 BASE-TX/FX 5-PORT CLASSII REPEATER CONTROLLER 1.0 FEATURES • Separate jabber and partition state machines for each port • On-chip elasticity buffer for PHY signal re-timing to the MX98746 clock source • Contents of internal register loaded from EEPROM

Contextual Info: MXIC _M X 9 8 7 4 2 FEBC 1 OO BASE FAST ETHERNET BRIDGE CONTROLLER 1.0 FEATURES 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging Minimum 16K byte, maximum 256K byte buffer memory Selectable TX/FX/T4 symbol-level repeater, Mil interfaces, and 10BASE serial port

MSA-7

Abstract: MSA10 MX98741 MX98743 RS10 RS11 RS12 6jm6 RS111 A MSA8
Contextual Info: MX98743 FEM 100 Base Fast Ethernet Management Chip 1.0 FEATURES * Support IEEE 802.3 MIBs * Support RMON etherStatsEnty and etherStats History group * 8/12/32 bit microprocessor interface * Linear mapped registers for easy programming * Embedded MAC for low-cost management functions implementation