TAG J3 Search Results

84118 latch

Contextual Info: GS84118T/B 256K x 18 Sync Cache Tag TQFP, BGA Commercial Temp Industrial Temp FEATURES • 3.3V +10%/-5% Core power supply, 2.5V or 3.3V I/O supply. • Intergrated data comparator for Tag RAM application. • FT mode pin for FLOW THROUGH or PIPELINE operation.

j182

Abstract: TSSOP10 J196 Transistor J182 if uhf modulator ATA5590 915 MHz RFID j182 transistor j191 chip antenna rfid UHF
Contextual Info: Antenna Matching for UHF – RFID Transponder ICs Overview To achieve high performance with regards to the read and write distance of a tag, it is essential that the tag–antenna design be matched to the ATA5590 input impedance, because the return link modulation of the ATA5590 uses PSK Phase Shift Keying .

B1-66

Contextual Info: GS84118T/B-166/150/133/100 166 MHz–100 MHz 8.5 ns–12 ns 3.3 V VDD 3.3 V and 2.5 V I/O 256K x 18 Sync Cache Tag TQFP, BGA Commercial Temp Industrial Temp Features • 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply • Intergrated data comparator for Tag RAM application

GS84118-2000207

Abstract: DQ116
Contextual Info: GS84118T/B-166/150/133/100 166 MHz–100 MHz 8.5 ns–12 ns 3.3 V VDD 3.3 V and 2.5 V I/O 256K x 18 Sync Cache Tag TQFP, BGA Commercial Temp Industrial Temp Features • 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply • Intergrated data comparator for Tag RAM application

Contextual Info: G MICRO" M ITSUBISHI L S ., .V \\^ Z > M 332 4 3G S -25 ,-3 0 CMOS TAG MEMORY M 32/TAG M DESCRIPTION M 3 3 2 4 3 G S -2 5 , -3 0 (M 3 2 /T A G M ) is 5 1 2 entry X 4 w ay PIN CONFIGURATION (BOTTOM VIEW) /1 0 2 4 entry X 2 w ay T A G M em o ry fa b ric a te d with a C M O S

Contextual Info: G m ic r o " t, 2 * H f l 2 a o a i s i H b . m h M its u b is h i l s i , M33243GS-25,-30 s« * • n iT S U B X S H iin ic n P T R /n iP R O ete d CMOS TAG MEMORY M 32/TA G M r^ z s -s > [ DESCRIPTION M33243GS-25, -30 (M 32/TAG M ) is 512 entry X 4 way

D425G

Abstract: ACT21 SN74BCT2166
Contextual Info: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs SCHS012-D3513, JUNE 1990-REVISED NOVEMBER 1991 SN74BCT2163, SN74BCT2164 Fast Address to MATCH Delay. 12 ns Max FM PACKAGE CTOP VIEW ’BCT2163 Has Totem-Pole Match Output Q\*~

SCAD002

Abstract: BCT2164
Contextual Info: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs _ D3513, JUNE 1990 — REVISED A U G U S T 1990 • Fast Address to MATCH Delay . . .12-ns Max • ’BCT2163 has Totem-Pole Match Output

TA114

Abstract: BWEB TA111 PC 2500H SA02 SA07 ta115 485Turbocache 82485M L486
Contextual Info: in te i 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Intel486 MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel

82485

Contextual Info: in te i 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Intel486 MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel

CSM 6850

Abstract: mg80960xa 80960XA BV EI 303 3628 80960CA 80960KA 80960KB 80960MC M8259A 77106
Contextual Info: 80960XA EMBEDDED 32-BIT MICROPROCESSOR WITH 33RD TAG BIT TO SUPPORT OBJECT-ORIENTED PROGRAMMING AND DATA SECURITY M ilita ry • Implements JIAWG 32-Bit ISA Standard ■ High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at

W22C

Abstract: S12301DS 5133S stp520 t12m256 T12M256A-12J UPC507 MITAC PC515 GP014
Contextual Info: MODEL : 5133S Revision 02A Table of Contents page 1 Cover Sheet Block Diagram 2 Central Processor Unit 3 North Bridge Part A & PBSRAM/TAG RAM 4 North Bridge Part B 5 System Memory 6 South Bridge 7 PCMCIA Controller & Socket 8 Audio Codec & Amplifier 9 Enhance IDE & FDD Connector

8kx1 RAM

Abstract: SN74BCT216012 D3512 SN74ACT2160 SN74BCT2160-12
Contextual Info: SN74BCT2160 8K x 4 2-WAY CACHE ADDRESS COMPARATOR/TAG RAM SCHS011 - D3512, JUNE 1990- REVISED MARCH 1992 Fast Address to Match Time. . . 12 ns Max IO Upgrade of the SN74ACT2160 FM PACKAGE TOP VIEW o • 't CO OJ 1- o < < < < < < Q 2-Way Architecture Significantly Improves

82485

Contextual Info: Â M © 1 DGsOF@K[MÄ¥D Kl J n te l DEC 05 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Ì486TM MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag

SiS 651 chipset

Abstract: SiS chipset TI HA04 logic diagram of 74LS245 SIS 651 128m simm 72 pin ide hardisk sis chipset ide pci to isa bridge Silicon Integrated System
Contextual Info: SiS5120 Pentium PCI/ISA Chipset 1. Introduction PBSRAM CPU Host Address Host Data Bus Tag RAM MD Bus 244 x 2 optional MA Bus Master IDE DRAM SiS5120 USB GPIO BIOS KBC 245 x2 or x4 PCI Bus ISA Bus ISA Device ISA Device ISA Device ISA Dev ice PCI Device PCI

82485

Abstract: EA0S PC 2500H tagram match SA010 SA09 TAI11 "Lookaside Cache"
Contextual Info: » ù n tg l 0 5 ¡991 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Ì 486 TM MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel

Contextual Info: m mmRF PraiiiKis m 140 Com m erce Drive M icrosem i Nfontgomeryville, PA 18936-1013 Tel: 215 631-9840 S D 1 4 9 5 RF & MICROWAVE TRANSISTORS 850-890MHz CLASS C, BASE STATIONS « « * , » » « CLASS C TRANSÌSTOR FREQUENCY 870MHz VOL TAG P 24V POWER OUT

"snoop filter"

Abstract: 82801DB E8870DH E8870SP snoop filter ITANIUM2 82870P2 E8870 E8870IO P64H2
Contextual Info: Intel E8870SP Scalability Port Switch SPS Datasheet Product Features • ■ ■ Scalability Port (SP): — Six SPs with 3.2 GB/s peak bandwidth per direction per SP. — Bi-directional SPs for a total bandwidth of 38.4 GB/s. Integrated Snoop Filter: — 1 MB 12-way set associative tag array

RAS 1210 SUN HOLD

Abstract: sun hold ras 1210 SiS5571 magnetic switch diagram push botton SiS chipset IRQ1-15 t85 ha6 HA2311 Silicon Integrated System HA25
Contextual Info: SiS5571 Pentium PCI/ISA Chipset 1. System Block Diagram PBSRAM CPU Host A ddress Host Data Bus Tag RAM MD Bus Master IDE MA Bus SiS5571 Keyboard DRAM USB PCI Bus ISA Bus ISA Device ISA D ev ice ISA Device Preliminary V2.0 December 9, 1996 ISA Device PCI Device

TVC501

Abstract: 011-0049-01 Sony Semiconductor Replacement Handbook 1991 TD3F14A TDS320 c3940 us federal cataloging h6-1 PG506A Gpib to tds 3000 DATA PRECISION 8200 VOLTAGE CALIBRATOR
Contextual Info: Instruction Manual TDS 310, TDS 320 & TDS 350 Two Channel Oscilloscopes 070-8568-04 Use this manual for TDS 310, TDS 320, and TDS 350 oscilloscopes with serial numbers B040100 and above. Instrument Serial Numbers Each instrument manufactured by Tektronix has a serial number on a panel insert or tag, or stamped on the

GS841E18A

Abstract: T3B5
Contextual Info: GS841E18AT/B-166/150/133/100 166 MHz–100 MHz 8.5 ns–12 ns 3.3 V VDD 3.3 V and 2.5 V I/O 256K x 18 Sync Cache Tag TQFP, BGA Commercial Temp Industrial Temp Features • 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply • Dual Cycle Deselect DCD

2SC734

Abstract: 2SA561 2SA5610 2SC734 Y transistor 2SC734 transistor 2SA561 2SA561-Y 2SC734 R
Contextual Info: v 'j3> P N P x f$+ -> r P C m 2SA561 SILICON PNP EPITAXIAL TRANSISTOR (PCT PROCESS) 0 D riv er S tag e A m p lifie r A p p lic atio n s • ¡ S i t E - e - f ; V ceo = —5 0 V (M in .) • ISfQ'SEE^'iS''' : VCE(sat) = —0.3V(M ax.) • 2SC734 i 3 y /. v 9 V K tz 'O

Contextual Info: Ä G S M A N G E O M [F iG M T D @ të 80960XA EMBEDDED 32-BIT MICROPROCESSOR WITH 33RD TAG BIT TO SUPPORT OBJECT-ORIENTED PROGRAMMING AND DATA SECURITY Military • On-Chip Memory Management Unit — 4 Gigabyte Linear Address Space per Task — 4 Kbyte Pages with Supervisor/User

Contextual Info: Z Z E frO I P S -o n %-n e DAT E DON NO. 26.Jan.2007 062114 REVISED FORM 14.May .2007 062960 REVISED T IT LE REV. 0 N iM V u a - & # ffiH I I DESCRIPTION APPD. &APPD. U E.MATSUMOTO A.ONO0AWA f i ÈÜ CHK. DR. N.SASANO eto. T.TAKESHITA ^^hí&Cé/tAgí^iír A