TACF Search Results

7C344-25

Abstract: C344 74HC CY7C344 Signal Path Designer C3445
Contextual Info: CY7C344 32-Macrocell MAX EPLD Features tional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the

31-oq

Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
Contextual Info: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

84-PIN

Abstract: CY7C341B
Contextual Info: CY7C341B y CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and

K12J

Abstract: 100-PIN CY7C346 CY7C346B f 7400
Contextual Info: CY7C346 CY7C346B 5T CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec­ tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346

c3431

Abstract: C3438 c3432 CY7C343 c3435 C343-8
Contextual Info: CY7C343 64-Macrocell MAX EPLD Features • • • • • • The CY7C343 contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks LABs connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one that

SFAI608G

Abstract: 601-G SFA1608 1607G otis Marking Losa SFA1603G
Contextual Info: TAIWAN SEMICONDUCTOR s SFA1601G - SFA1608G 16.0 AMPS. Glass Passivated Super Fast Rectifiers tò RoHS T.QL-2 2 QAC COMPLIANCE . | 85M .7Q| 17fif4 4 4 1 n*A J14^-t ÜLLilü Ja=. JSSLLL& 11.V9 S7 04 y 1 14) inson?) •S34|'1SI> '.ilSi'.t-1) Features '> '> ❖

802G

Abstract: SF801G SF808G S01C
Contextual Info: TAIWAN s ' SF801G - SF808G SEMICONDUCTOR tò RoHS 8.0 AMPS. Glass Passivated Super Fast Rectifiers COM PLIANCE T0-220AB - Features High efficiency, lew VF High current capability High reliability Hig h su rge cu rre n t ca pabi lily Low po w e r loss. F o r use In lew vollag e. high frequency Inventor, free

fuji IGBT

Abstract: 6MBP150RA060
Contextual Info: FUJI 3 . - y n ? ? h FUJI NEW SEMICONDUCTOR PRODUCTS IGBT-IPM I ÍS M IP M -N y n tu K a rD S D e 6 0 0 V /1 5 0 A /6 in one-package R series 6MBP150RA060 Features V - X t S & 1 4 < 7 th Z r t y t r - y IG B T 5 1 7 y < r> T \ et z m m m i t Low power loss and soft switching

c341 transistor

Abstract: 7C341 diode c341 CY7C341 84-PIN C341
Contextual Info: 41 CY7C341 192-Macrocell MAX EPLD Features • • • • • • 192 macrocells in 12 LABs 8 dedicated inputs, 64 bidirectional I/O pin 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 expander product terms Available in 84-pin HLCC, PLCC, and PGA packages

Contextual Info: ADVANCE M in P n M I - MT4LC16270 256K X 16 DRAM DRAM 256K x 16 DRAM 3.3V EDO PAGE MODE FEATURES • Single +3.3V ±0.3V power supply* • Industry-standard xl6 pinouts, timing, functions and packages • High-performance CMOS silicon-gate process • Low power, 0.3mW standby; 165mW active, typical

MT4C16256DJ-7

Contextual Info: lU IIÖ Q ö lX I I techno lo g y. iN t MT4CÎ6256/7* 256K X 16 DRAM DRAM 256Kx 16DRAM FAST PAGE MODE FEATURES • Industry-standard x l6 pinouts, timing, functions and packages • High-perform ance CMOS silicon-gate process • Single +5V ±10% pow er supply*

Contextual Info: Ether Module -EM2C 10Base-2 Technology, Incorporated Ethernet Transceiver Module with on Board Isolation Transformer & DC/DC Converter A p ril 1994 Introduction The Thin N e t C heapernet m odule p ro vid e s a com plete L o c a l A re a N e tw o rk in terfa ce fo ra station, w itho u t a tra n s­

ne 5555 timer

Contextual Info: Lj 3 E ì> ñin233 ÜG03Ô2E S14 « S E E SEEÛ TECHNOLOGY INC Technology, Incorporated 1024K High Speed EEPROM Ju ly 1992 Features • Military, Extended and Commercial Temperature Rangea • -S 5°C to +125°C Operation Military • -4 0 °C to +85°C Operation (Extended)

transistor c343

Abstract: c343 diode lattice im4a3 CY7C343
Contextual Info: CY7C343 64-Macrocell MAX EPLD Features • • • • • • The CY7C343 contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks LABs connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one that

V442

Contextual Info: ADVANCE MICRON I m “ rn,“f,.T M T24D836 8M EGX 36, 16 M EGX 18 D R A MM O D U LE DRAM MODULE 8 MEG X 36,16 MEG x18 NEW I FAST PAGE MODE FEATURES PIN ASSIGNMENT Top View OPTIONS 72-Pin SIMM ( 1 - 22) MT24D836M/G nfmrnTTmTtmrnnTrnrrrrm MARKING • Timing

Contextual Info: PRELIMINARY MICRON 4 MEG DRAM MODULE X MT16LD464(X 64 DRAM MODULE 4 MEG x 64 32 MEGABYTE, 3.3V, FAST PAGE OR EDO PAGE MODE FEATURES • JEDEC- and industry-standard pinout in a 168-pin, dual-in-line m em ory m odule (DIMM) • H igh-perform ance CM OS silicon-gate process

umt block diagram

Abstract: pci365 uPC1397C upc1397 CRT TV BLOCK DIAGRAM PU15C PC1397C pci365C
Contextual Info: B IP O L A R A N A LO G INTEGRATED CIRCUIT _ /¿ P C 1 3 9 7 C A N A L O G I N T E R F A C E C I R C U I T FO R T E L E T E X T S Y S T E M The *iP C 1 3 9 7 C it a m onolithic inte grat'd circuit for the interface stage between the external analog signals and chroma

TFK 404

Abstract: T1S58 BCI83L Germanium diode OA 182 TFK diode transistors 2n 945 v744 akai amplifier tis62 BCI09
Contextual Info: S IL IC O N T R A N S IS T O R S PN P Fast Switches N PN Fast: Switches D e v ic e B S X 27 T IS 4 4 T IS 45 T IS 46 T IS 47 T IS 48 T IS 49 Page 96 166 168 170 172 172 174 D e v ice Page T I S 51 T IS 52 T IS 55 2N 706A 2N 708 2N 753 2N 914 178 180 185 317

F-91300

Abstract: D-8012 24LH02 F91300 MASSY
Contextual Info: m i 7 1992 24LH02 M icrochip 2K CMOS Serial EEPROM - High Endurance FEATURES DESCRIPTION • Single supply with operation from 6.0 V down to 2.0 V • Low power CMOS technology — 3 mA active current at 6.0 V — 50 jiA standby current at 6.0 V — 15 jiA standby current at 2.0 V

marking code AANG

Abstract: NT77 MT4C4256 2S650
Contextual Info: ADVANCE MT42C8255 TICittiOLOC' MC 2 MEG VRAM 256K x 8 DRAM WITH 5 1 2 x 8 SAM FEATURES • • • • • • • • • • • Industry standard pinout, timing, and functions High-performance, CMOS silicon-gate process Single +5V ±10% power supply Inputs and outputs are fully TTL compatible

v9511

Abstract: T1464
Contextual Info: PRELIMINARY 4 MEG x 64 DRAM MODULE 32 MEGABYTE, 3.3V, OPTIONAL SELF REFRESH, FAST PAGE OR EDO PAGE MODE FEATURES • JEDEC- and industry-standard nout in a 168-pin, dual-in-line memory m odule E IVIM) • High-performance CMOS silico i -gate process • Single +3.3V ±0.3V power supply• All device pins are TTL-compat ,ble

c3415

Abstract: cy7c341-30jc CY7C341
Contextual Info: CY7C341 y CYPRESS Features • • • • • • 192 macrocells in 12 LABs 8 dedicated inputs, 64 bidirectional I/O pin 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 expander product terms Available in 84-pin HLCC, PLCC, and PGA packages

Contextual Info: bM27S25 004203b ^70 A T A SHEET EC MOS INTEGRATED CIRCUIT /¿PD42S4190, 424190 4 M-BIT DYNAMIC RAM 256K-WORD BY 18-BIT, FAST PAGE MODE, BYTE WRITE MODE DESCRIPTION The //PD42S4190, 424190 are 262 144 w ords by 18 bits dynamic CMOS RAMs. The fast page m ode and byte

74HC

Abstract: 7C344 CY7C344 CY7C344B LTAC01
Contextual Info: CY7C344 CY7C344B i f CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins