T894 Search Results

SI 122 D

Abstract: AS12E
Contextual Info: M I T E L SEMICONDUCTOR 15E D I b54T37Q OOOM'iflB 2 I MITEL* T8940 T1/CEPT Digital Trunk PLL ISO-CMOS ST-BUS FAM ILY 91 61-002-03S-N A ISSU E 3 Features Provides T1 clock a t 1.544 M Hz locked to input fram e pulse. So u rces C EP T 30 + 2 D ig ital T ru n k/S T -B U S

Contextual Info: MH89760 T1/ESF Framer & Interface S T -B U S " F A M IL Y M IT E L 9 1 6 1 -0 0 2 -064-N A _ ISSUE 5_ O cto ber 1989 Features • • • • • • • • • • • • • • • C o m p le te in te rfa c e t o a b id ire c tio n a l T1 lin k .

Contextual Info: CMOS ST-BUS FAMILY MITEL MT8985 Enhanced Digital Switch Features ISSUE 5 M arch 1997 Ordering Inform ation • 256 x 256 channel non-blocking switch MT8985AE MT8985AP M T8985AL P rogram m able fram e integrity for w ideband channels 40 Pin Plastic DIP

Contextual Info: CMOS ST-BUS FAMILY 04Hitel T8941 Advanced T1/CEPT Digital Trunk PLL Features July 1993 Ordering Inform ation • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock fram e pulse • Provides CEPT c lo ck at 2.048 M Hz and ST-BUS clock and tim ing signals locked to an internal or

MD65SC51

Abstract: T50D TSD50 SLC 4002 CFS2575 MH89760 MH89761 MT8940 SLC96 TFS2573
Contextual Info: M IT E L 9 MH89760 T1/ESF Framer & Interface ST-BUS - FAM ILY 9 1 6 1 -0 0 2 -064-N A ISSUE 5 Features C o m p le te in te r fa c e t o a b id ir e c tio n a l T1 lin k . ST-BUS c o m p a tib le . D 3 / D 4 o r ESF f r a m in g a n d SLC-96 c o m p a tib le .

Contextual Info: | W l| - r P | IV ll E . I- MT8977 J1/ESF Framer Circuit A C CU N ET T 1.5 ISO -CM O S ST-BUS'" FAM ILY Preliminary Information 9161-002-164-N A_ ISSUE 1_ July 1993 Features • D3/D4 o r ESFfram in g and SLC-96 com patible

Contextual Info: MITEL* MH89790 CEPT PCM 30/CRC-4 Framer & Interface ST -B U S" F A M IL Y Prelim inary In fo rm a tio n 9161-002-080-N A ISSUE 4 Features Pin Connections Com plete prim ary rate 2048 kbit/s CEPT transceiver w ith CRC-4 option. Selectable HDB3 or A M I line code.

Contextual Info: T8941 Advanced T1/CEPT Digital Trunk PLL CMOS ST-BUS " FAMILY MITEL 9161-002-132-NA Features ISSUE 5 July 1993 Ordering Information • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock frame pulse • Provides CEPT clock at 2.048 MHz and ST-BUS

slc 500 circuit diagram

Abstract: MH89761 MT8952 MT8976 MT8976AE MT8976AP MT8977 MT8979 MT8980 mark l8r
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8976 T1/ESF Framer Circuit g M ITEL S E M IC O N D U C T O R Features ISSUE 11 O ctober 1997 O rdering Inform ation • D3/D4 or ESF fram ing and S LC -96 com patible • 2 fram e ela stic buffer w ith 32 usee jitte r buffer

htc hd2 schematic

Abstract: KBC-M38857 r2561 h946 D2041 C3931 L5631 ASUS RN10B smd diode a3l
Contextual Info: 5 4 3 2 1 FILE LIST THERMAL A3 BLOCK DIAGRAM D 05 POWER IMVP4 BANIAS 24.5W FAN 35 03 37 38 39 40 41 42 43 44 45 04 PSB C North Bridge DDR A3N 855GM 266 A3L 852GM 266 CPU Celeron/ Banias/ Dothan(400) Celeron/ Banias/ Dothan(400) Celeron/ Banias/ Dothan(400)

Contextual Info: ISO-CMOS ST-BUS FAMILY MT8976 T1/ESF Framer Circuit g M ITEL S E M IC O N D U C T O R Features ISSUE 11 O ctober 1997 O rdering Inform ation D3/D4 or ESF fram ing and S LC -96 com patible 2 fram e elastic buffer w ith 32 |a,sec jitte r buffer M T8976AE

Contextual Info: ST-BUS FAMILY MITEL* MH89760B T1/ESF Framer & interface Preliminary Information Features ISSUE 5 C om plete interface to a bidirectional T1 link D3/D4 or ESF fram ing and SLC -96 com patible Two fram e elastic buffer w ith 32 jis jitte r buffer Insertion and detection of A, B, C, D bits

Contextual Info: •I MITEL' b24^37G DDÜ7S7G SÔ2 « M I T C T8940 T1/CEPT Digital Trunk PLL ISO-CMOS ST-BUS FAMILY Features April 1992 ISSUE 6 9161-002-035-NA Pin Connections Provides T1 clock at 1.544 M Hz locked to input fram e pulse. Sources C EP T 3 0 + 2 D ig ital T ru n k /S T -B U S