B2MT37D Search Results

Contextual Info: ISO-CMOS ST-BUS FAMILY MITEL* HDLC Protocol Controller Features • MT8952B _ ISSUE 5_May 1995 Formats data as per X.25 CCITT level-2 standards Ordering Information MT8952BC 28 Pin Ceramic DIP MT8952BE 28 Pin Plastic DIP

537D

Abstract: 00LQ MT8980DC
Contextual Info: ISO-CMOS ST-BUS FAMILY MITEL* MT8980D Digital Switch Features May 1995 • Mitel ST-BUS compatible • 8-line x 32-channel inputs • 8-line x 32-channel outputs • 256 ports non-blocking switch • Single power supply +5 V • Low power consumption: 30 mW Typ.

Contextual Info: MITEL MT9075 E1 Single Chip Transceiver Preliminary Information Features • ISSUE 2 C om bined PCM 30 fram er, Line Interface Unit LIU and link controllers in a 68 pin PLCC or 100 pin MQFP package • S electable bit rate data link access with optional S a bits HDLC con tro ller (HDLCO) and

Contextual Info: is o 2-c m o s s t - b u s f a m ily MITEL* MT9092 Digital Telephone with HDLC HPhone-ll Features _ISSUE 2_May 1995 • Programmable p-Law/A-Law codec and filters • Programmable CCITT (G.711)/sign-magnitude coding

Contextual Info: b 2 ^ 3 7 D 0007b23 bM7 • M I T C MT8880C/MT8880C-1 Integrated DTMF Transceiver is o 2-c m o s MITEL Preliminary Information 9161-002-032-NA Features • • • • • • • c GS VRtf VSS OSC1 Li 20 H VDD 19 3 St/GT 18 J ESt 17 2 D3 16 'J D2 15 J D1

Contextual Info: CMOS ST-BUS FAMILY 04Hitel MT8941 Advanced T1/CEPT Digital Trunk PLL Features July 1993 Ordering Inform ation • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock fram e pulse • Provides CEPT c lo ck at 2.048 M Hz and ST-BUS clock and tim ing signals locked to an internal or

Contextual Info: CMOS ST-BUS FAMILY MT8941 Advanced T1/CEPT Digital Trunk PLL MITEL Features ISSUE 5 July 1993 Ordering Information • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock frame pulse • Provides CEPT clock at 2.048 MHz and STBUS clock and timing signals locked to an

Contextual Info: • «%/ I I b5HT37Q QQQ74bl b n ■ H IT C MT88V32 8 x 4 High Performance Video Switch Array * Advance Information Vf'*'*' '*. i- iv ^ y v ic w iiw :. M ■ y-i 9161-002-161-NA_ ISSUE 4_ April 1993 Features • 32 bidirectional CMOS "T" switches in an 8X4

Contextual Info: • b S *n 3 7 Q ^ f iT « M IT C MT8982 Small Digital Switch MiniDX ISO-CMOS ST-BUS FAM ILY M ITEL’ Features • ST-BUS/GCI com patible switch m atrix. • 64 channel non-blocking tim e switch. • 2 x 32 channel serial inputs and outputs. • Per-channel tristate control.

Contextual Info: ISO-CMOS ST-BUS FAMILY MITEL* MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 7 July 1993 Ordering Information • Provides T1 clock at 1.544 MHz locked to input frame pulse • Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

Contextual Info: M T 9 0 2 1 0 M ITEL Multi-Rate Parallel Access Circuit Preliminary Information Features • • • • • • • ISSUE 1 Parallel-to-serial and serial-to-parallel conversion of up to 1536 full duplex channels or 3072 time-slots Serial port data rates selectable between 2.048,

Contextual Info: MT90840 M ITEL Distributed Hyperchannel Switch Preliminary Information Features • Time-slot interchange function between eight pairs of ST-BUS/GCI/MVIP streams 512 channels and a Parallel Data Port (PDP) • Parallel port data rates up to 19.44 Mbyte/s