T35A Search Results

Asus MONITOR MOTHERBOARD CIRCUIT MANUAL

Abstract: T2D 83 diode gp026 st GP025 82430TX 82371EB Asus PC MOTHERBOARD CIRCUIT schematic diode T75A Asus PC MOTHERBOARD CIRCUIT MANUAL 8272A floppy disk controller block diagram
Contextual Info: PRELIMINARY DRAFT Intel Extended Temperature 82371EB PCI-TO-ISA/IDE Xcelerator PIIX4E Datasheet  Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers  Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation Supported Kits for both Pentium and

Contextual Info: MF1501-02 IEEE1394 Controller S1R72805 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

Contextual Info: intJ. 82375EB PCI-EISA Bridge PCEB Provides the Bridge Between the PCI Bus and EISA Bus 32-Bit Data Paths 100% PCI and EISA Compatible — PCI and EISA Master/Slave Interface — Directly Drives 10 PCI Loads and 8 EISA Slots — Supports PCI at 25 MHz to 33 MHz

82378ib

Contextual Info: A P M Ä M ! DM iP© I^[ìfflA'irD@ N] in te i 82378IB SYSTEM I/O SIO Provides the Bridge Between the PCI Bus and ISA Bus Arbitration for PCI Devices — Four PCI Masters are Supported — Fixed, Rotating, or a Combination of the Two 100% PCI and ISA Compatible

PIR D 203 S

Abstract: BRQ TI 78 RA16 UT69R000 t37h
Contextual Info: Standard Products UT69R000 Rad-Hard MicroController Data Sheet January 1998 q Built-in 9600 baud UART q Full military operating temperature range, -55oC to +125oC, in accordance with MIL-PRF-3853 for Class Q or V q Radiation-hardened process and design; total dose

TTC-B01

Abstract: TTC-B-01 TTC 104 T5.5A ttc 103 MA28139 ttc 103 datasheet FTC 960 GEC Plessey Semiconductors cross reference RTU DATA SHEET
Contextual Info: MA28139 MA28139 OBDH Bus Terminal Replaces June 1999 version, DS3592-5.0 DS3592-6.0 January 2000 The OBT ASIC will interface any user to the ESA On Board Data Handling bus. Developed under ESA Contract, it conforms to ESA OBDH, Digital Bus Interface and Internal

T3D 34 diode

Abstract: 82440LX Diode T3D 57 t57b T27b t59b T31C Transistor t59c ISA BUS spec t119
Contextual Info: E DATASHEET ADDENDUM 82371AB PIIX4 PCI ISA IDE Xcelerator Timing Specifications September 1997 Order Number: 290548-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions

TI8A

Abstract: LA7390N T28A T31A VR33 VR36 OSD ic T14A dg t3a
Contextual Info: Ordering number: EN 39528 M o n o lilh ic L inear 1C LA7390N No. 3952B SA\YO VHS-format VCR Video Signal Processor I Overview Package Dlm§ffdony|¡ The LA7390N is a single-chip video signal processing IC that is compatible with three systems. 3170-DIP36S

82335

Abstract: intel 82230
Contextual Info: in te i 82335 SX HIGH-INTEGRATION INTERFACE DEVICE FOR 386 SX MICROPROCESSOR BASED PC-AT SYSTEMS • Operates with the 8 2 2 3 0 and 8 2 2 3 1 to Provide 1 0 0 % IBM ATtm Compatibility ■ ■ Optimized for 16 MHz and 2 0 MHz SX Microprocessor Based PC-AT

SMD MARKING CODE A00b

Abstract: mil-std-1750a MARKING CODE A00B MIL-PRF-38510 as3 SMD Transistor MIL-STD-1750 ttl nim marking a00b SMD A009 pir chip
Contextual Info: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet May 2003 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA) q Supports MIL-STD-1750A 32-bit floating-point

5757H

Abstract: A1318 U DP83905
Contextual Info: S e m i c o n d u c t o r DP83905 AT/LANTIC AT Local Area Network Twisted-Pair Interface Controller General Description Features The AT/LANTIC AT Local Area Network Twisted-pair Inter­ face Controller is a CMOS VLSI device designed for easy implementation of CSMA/CD local area networks.

epson 0x95

Abstract: CBW15 S1R72003F00B100 CBW18 equivalent transistor t205 t324 t393 transistor t349 00A1 CS01
Contextual Info: MF1495-02 USB2.0 Device Controller S1R72003 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

VG-468

Abstract: vadem vg-468 386SL vg-365 LIM EMS 4.0 VG468 82365SL SA12 82365 pcmcia SA14
Contextual Info: VADEM VADEM VG-468 PC CARD SOCKET CONTROLLER D ATA M A N UA L DECEMBER 1993 REV. 02 M151017-02 Copyright 1992 Vadem All Rights Reserved Information furnished by Vadem is believed to be accurate and reliable. However, no responsibility is assumed by Vadem for its use; nor for any infringements of patents or other rights of third parties

TTC-B-01

Abstract: TTC 104 ttc 103 datasheet MA28138 MA28139 marconi company MIL-STD-1750 MOSC T5.5A
Contextual Info: MA28139 MA28139 OBDH Bus Terminal Replaces January 2000 version, DS3592-6.0 DS3592-6.1 July 2002 The OBT ASIC will interface any user to the ESA On Board Data Handling bus. Developed under ESA Contract, it conforms to ESA OBDH, Digital Bus Interface and Internal

1FT57

Abstract: T71A 27MHz-LPF SA-2R VREG25 LSI100 T17 6PIN T35A
Contextual Info: 注文コード No.N A 1 6 1 0 A 半導体データシートNo.NA1610をさしかえてください。 Bi-CMOS 集積回路 DVD レコーダの映像・ 音声信号入出力インタフェース用 LV71081E 概要 LV71081EはDVDレコーダの映像・音声信号入出力インタフェースICである。

IMP82C206

Abstract: 5Z33 memory mapper 2412b0
Contextual Info: INTNTL m C R O E L C T N 47E D • 1405042=] GDG1123 543 ■ IMP mm T ' ò 2 - ' ò ^ - \ tò IMP82C206 Features IMP82C206 — Integrated Peripherals Controller ■ Compatible with IBM PC/AT ■ Provides the fully-compatible equivalent of Intel's 8237 DMA

Contextual Info: MF1501-02 IEEE1394 Controller S1R72805 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

CHIP T395 S

Abstract: S1R72103
Contextual Info: MF1528-01 SCSI-2/IDE Interface Controller S1R72103 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

S1R72901F00A1

Abstract: MF1504-02
Contextual Info: MF1504-02 IEEE1394 Controller S1R72901 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

temperature controller CHB 402 pid

Abstract: temperature controller CHB 402 manual IC 74115 LS 74141 pin diagram of ic 7489 IC 74134 S1R72V05F00 74118 CHN 844 diode
Contextual Info: S1R72V05 Technical Manual Rev.1.3 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material

VIA SL9011

Contextual Info: The FlexSet PC/AT System Controller SL9011 PRELIMINARY FEATURES • AT System Control Logic. • Supports 80286,80386SX P9 , or 80386DX-based Designs. • Up to 25 MHz Performance. • Clock Switching and Reset Logic. • Programmable Wait States for 8 Bit AT Cycles.

B1189

Abstract: mil-std-1750a MME transistor 401 4AX4 MIL-STD-1750 STD-1750A SI T37B t34l UT1750AR
Contextual Info: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet November 2000 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA)

MA28139

Abstract: MA28138 T5.5A TTC-B01
Contextual Info: MA28139 MA28139 OBDH Bus Terminal Replaces January 2000 version, DS3592-6.0 DS3592-6.1 July 2002 The OBT ASIC will interface any user to the ESA On Board Data Handling bus. Developed under ESA Contract, it conforms to ESA OBDH, Digital Bus Interface and Internal

T55B

Abstract: T71A t19c t17c t61b t58b t57b T27b t65a T3D 62
Contextual Info: 82371AB PCI ISA IDE Xcelerator PIIX4 23.0 Clock, Reset, ISA Bus, X-Bus, and Host Timing Diagrams Figure 41. Clock Timing Period High Time PCICLK, SYSCLK, OSC 2.0V 0.8V Low Time Fall Time Rise Time Figure 42. Reset Inactive Timing SUS_STAT[1:2]# t2f PCIRST#, RSTDRV