T20 VER 2 Search Results

PD45128163

Abstract: uPD45128163G5-A10I-9JF uPD45128163G5-A10LI-9JF uPD45128163G5-A75I-9JF uPD45128163G5-A75LI-9JF uPD45128163G5-A80I-9JF uPD45128163G5-A80LI-9JF PD45128163-I
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD45128163-I 128M-bit Synchronous DRAM 4-bank, LVTTL WTR Wide Temperature Range Description The µPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152 x 16 × 4 (word × bit × bank).

PD45128163

Abstract: uPD45128163G5-A75-9JF-E
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD45128163-E 128M-bit Synchronous DRAM 4-bank, LVTTL Description The µPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152 x 16 × 4 word × bit × bank . The synchronous DRAM achieved high-speed data transfer using the pipeline architecture.

PD45128163

Abstract: PD45128163G5-A10-9JF PD45128163G5-A75-9JF PD45128163G5-A75A-9JF PD45128163G5-A75L-9JF PD45128163G5-A80-9JF PD45128163G5-A80L-9JF
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD45128163 128M-bit Synchronous DRAM 4-bank, LVTTL Description The µPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152 x 16 × 4 word × bit × bank . The synchronous DRAM achieved high-speed data transfer using the pipeline architecture.

uPD45128163G5-A75LT-9JF

Abstract: PD45128163 uPD45128163G5-A10LT-9JF uPD45128163G5-A10T-9JF uPD45128163G5-A75T-9JF uPD45128163G5-A80LT-9JF uPD45128163G5-A80T-9JF PD45128163-T
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD45128163-T 128M-bit Synchronous DRAM 4-bank, LVTTL WTR Wide Temperature Range Description The µPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152 x 16 × 4 (word × bit × bank).

PD45128163

Abstract: uPD45128163G5-A75I-9JF-E uPD45128163G5-A75LI-9JF-E
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD45128163-I-E 128M-bit Synchronous DRAM 4-bank, LVTTL WTR Wide Temperature Range Description The µPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152 x 16 × 4 (word × bit × bank).

Contextual Info: DATA SHEET 128M bits Mobile RAM EDL1216CASA 8M words x 16 bits Description Pin Configurations The EDL1216CA is a 128M bits Mobile RAM organized as 2,097,152 words × 16 bits × 4 banks. The Mobile RAM achieved low power consumption and high-speed data transfer using the pipeline architecture. All inputs

Contextual Info: DATA SHEET 128M bits Mobile RAM EDL1216AASA 8M words x 16 bits Description Pin Configurations The EDL1216AA is a 128M bits Mobile RAM organized as 2,097,152 words × 16 bits × 4 banks. The Mobile RAM achieved low power consumption and high-speed data transfer using the pipeline architecture. All inputs

Contextual Info: DATA SHEET 128M bits Mobile RAM EDL1216CASA 8M words x 16 bits Description Pin Configurations The EDL1216CA is a 128M bits Mobile RAM organized as 2,097,152 words × 16 bits × 4 banks. The low power synchronous DRAMs achieved low power consumption and high-speed data transfer using the

Contextual Info: DATA SHEET 128M bits Mobile RAM EDL1216BASA 8M words x 16 bits Description Pin Configurations The EDL1216BA is a 128M bits Mobile RAM organized as 2,097,152 words × 16 bits × 4 banks. The low power synchronous DRAMs achieved low power consumption and high-speed data transfer using the

Contextual Info: DATA SHEET 128M bits Mobile RAM EDL1216BASA 8M words x 16 bits Description Pin Configurations The EDL1216BA is a 128M bits Mobile RAM organized as 2,097,152 words × 16 bits × 4 banks. The Mobile RAM achieved low power consumption and high-speed data transfer using the pipeline architecture. All inputs

EDL5132CBMA

Abstract: b008m
Contextual Info: PRELIMINARY DATA SHEET 512M bits Mobile RAM MCP 2 pcs of 256Mb components EDL5132CBMA 16M words x 32 bits Description Pin Configurations The EDL5132CBMA is a 512M bits Mobile RAM MCP (Multi Chip Package) organized as 4,194,304 words × 32 bits × 4 banks, 2 pieces of 256M bits Mobile RAM in

Contextual Info: DATA SHEET 128M bits Mobile RAM EDL1216AASA 8M words x 16 bits Description Pin Configurations The EDL1216AA is a 128M bits Mobile RAM organized as 2,097,152 words × 16 bits × 4 banks. The low power synchronous DRAMs achieved low power consumption and high-speed data transfer using the

2SD187

Abstract: 2SD348 25D40 c 50275 2SD186 2SD313 2SD314 2SD331 2SD353 2sd400
Contextual Info: Type Number •a o> s *■ *3 4 C 00 OS •2 « Q cl. A pplications ca> E 8 *5. o ai 2SD30 LF Power Amp 2SD67 LF Power Amp «> | 3 O Si <3 - V -,m G, AL 40 S, ME 120 2SD68 LF Power Amp - S, ME 75 2SD72 LF Power Amp - G, AL 25 2SD72 LF Power Amp - G, AL

EDL6416BABH-75-E

Abstract: edl6416
Contextual Info: PRELIMINARY DATA SHEET 64M bits Mobile RAM EDL6416BABH 4M words x 16 bits Description Pin Configurations The EDL6416BABH is a 64M bits Mobile RAM organized as 1,048,576 words × 16 bits × 4 banks. The Mobile RAM achieved low power consumption and high-speed data transfer using the pipeline

Contextual Info: DATA SHEET 1G bits XDR DRAM EDX1032BBBG 32M words x 32 bits Overview Features The EDX1032BBBG is 1G bits XDR DRAM organized as 32M words × 32 bits. They are general-purpose high-performance memory devices suitable for use in a broad range of applications.

AA15

Abstract: AB16 AB17 EP1K100
Contextual Info: EP1K100 Device Pin-Outs ver. 1.0 Pin Name 1 MSEL0 (2) MSEL1 (2) nSTATUS(2) nCONFIG (2) DCLK (2) CONF_DONE (2) INIT_DONE (3) nCE (2) nCEO (2) nWS (4) nRS (4) nCS (4) CS (4) RDYnBSY (4) CLKUSR (4) DATA7 (4) DATA6 (4) DATA5 (4) DATA4 (4) DATA3 (4) DATA2 (4)

EPF6016

Abstract: 216 C9 T20 ver 2
Contextual Info: EPF6016 Device Pin-Outs ver. 1.0 Pin Name 1 144-Pin TQFP EPF6016 208-Pin PQFP EPF6016 240-Pin PQFP EPF6016 256-Pin BGA EPF6016 MSEL (2) 33 46 52 T3 nSTATUS (2) 56 80 92 W11 nCONFIG (2) 53 77 89 Y11 DCLK (2) 128 184 212 C10 CONF_DONE (2) 105 150 172 E18 INIT_DONE (3)

EPF6024A

Contextual Info: EPF6024A Device Pin-Outs ver. 1.0 Pin Name 1 144-Pin TQFP EPF6024A 208-Pin PQFP EPF6024A 240-Pin PQFP EPF6024A 256-Pin BGA EPF6024A 256-Pin FineLine BGA EPF6024A MSEL (2) 33 46 52 T3 L5 nSTATUS (2) 56 80 92 W11 K8 nCONFIG (2) 53 77 89 Y11 N8 DCLK (2) 128

2SB185

Abstract: 2SB187 2sb22 2sb186 2sb303 2sb342 2SB375A 2SB273
Contextual Info: 3 O g 03 Electrical Characteristics/Ta=25°C Absolute Maximum Ratings/Ta=25°C Vc' bo Veto t VfEH Vkbh I, P, «L I kbo 1<BC> Ve« max VKB max VcK I, - 100- 560 6 lm 110 10 2.2 60- 320 10 10m 130 10 3.2 20 15 /i 6 12/1 1.5 100m - 67-330 - - - - - i : With

AA13

Abstract: AA15 AB16 EP1K50 AA11AA13
Contextual Info: EP1K50 Device Pin-Outs ver. 1.0 Pin Name 1 MSEL0 (2) MSEL1 (2) nSTATUS (2) nCONFIG (2) DCLK (2) CONF_DONE (2) INIT_DONE (3) nCE (2) nCEO (2) nWS (4) nRS (4) nCS (4) CS (4) RDYnBUSY (4) CLKUSR (4) DATA7 (4) DATA6 (4) DATA5 (4) DATA4 (4) DATA3 (4) DATA2 (4)

484-pin BGA

Abstract: AA13 AA15 AB16 EPF10K30E
Contextual Info: EPF10K30E Device Pin-Outs ver. 1.0 Pin Name 1 MSEL0 (2) MSEL1 (2) nSTATUS (2) nCONFIG (2) DCLK (2) CONF_DONE (2) INIT_DONE (3) nCE (2) nCEO (2) nWS (4) nRS (4) nCS (4) CS (4) RDYnBUSY (4) CLKUSR (4) DATA7 (4) DATA6 (4) DATA5 (4) DATA4 (4) DATA3 (4) DATA2 (4)

diode t25 4 H9

Abstract: diode t25 4 L9 diode t25 4 k6 diode t25 4 k8 diode t25 4 G9 diode t25 4 F8 diode t25 4 B9 diode t25 4 g8 diode t25 4 F7 diode t25 4 L8
Contextual Info: Pin Information For The Stratix EP1S10 Device, ver 3.7 Note 2 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B1 B1 B1 B1 B1 B1 B1 B1 B1

AA13

Abstract: AA15 AB16 EPF10K30E
Contextual Info: EPF10K30E Device Pin-Outs ver. 1.0 Pin Name 1 MSEL0 (2) MSEL1 (2) nSTATUS (2) nCONFIG (2) DCLK (2) CONF_DONE (2) INIT_DONE (3) nCE (2) nCEO (2) nWS (4) nRS (4) nCS (4) CS (4) RDYnBUSY (4) CLKUSR (4) DATA7 (4) DATA6 (4) DATA5 (4) DATA4 (4) DATA3 (4) DATA2 (4)

diode t25 4 H9

Abstract: diode t25 4 L9 diode t25 4 G9 diode t25 4 j3 diode t25 4 k8 diode t25 4 k6 diode AA19 diode T25 4 F8 diode t25 4 g8 diode t25 4 L5
Contextual Info: Pin Information For The Stratix EP1S20 Device, ver 3.6 Note 2 Bank Number VREF Bank Pin Name/Function Optional Function(s) B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2