T00344 Search Results

Contextual Info: H ig h P erform a n ce 32 K X 16 CMOS SRAM A S7C 513 A S 7 C 3 5 13 3 2 K x 16 CMOS SRAM • T T L - c o m p a tib le , th r e e - s ta te I / O • H ig h s p e e d • 4 4 - p i n JEDEC s ta n d a r d p a c k a g e - 4 0 0 m i l SO J - 1 0 / 1 2 / 1 S / 2 0 n s a d d r e s s a c c e ss tim e

Contextual Info: H ig h P e r f o r m a n c e 64K X 8 3.3V CM OS SRAM A S 7 C 3 5 12 X Low voltage 6 4 K x 8 CM O S SRAM • O rganization: 6 5 ,5 3 6 w ords x 8 bits • Single 3.3 ± 0.3V p o w er supply • H igh speed - 2 0 /2 5 ns address access tim e - 5 / 6 ns o u tp u t enable access tim e

4lc1m16e5-6

Contextual Info: H ig h P e r f o r m a n t e lM x 16 CM OS DRAM » H A S4C 1M 16E 5 A S4L C 1M 16E 5 A 1 M X 16 CMOS EDO DRAM Preliminary information Features • O rg a n iz a tio n : 1,048,576 w o r d s x 16 b its • 1 0 2 4 re fre s h cycles, 16 m s re fre s h in terv al

Contextual Info: I l i ^ h l*i i loi i n ,iih c S I 2k x X r>V C M O S Ma sh MiPKOM •■ \ S 2 >M 40 A S I ?.KX<S CMOS f ldsli I I f'KOM Preliminary information Features • Low power consumption • Organization: 512KX8 • Sector architecture - 3 0 m A m a x im u m re a d c u rre n t

as4c256k16eo

Abstract: 256KX16 AS4C256K16E0 LO301
Contextual Info: H ig h P e r fo r m a n c e 256K X 16 CM OS DRAM A S4C 256K 16E 0 A 2 5 6 K X 1 6 CM O S EDO DRAM Preliminary information Features • Extended data out • 512 refresh cycles, 8 ms refresh interval • Organization: 26 2 ,1 4 4 words X 16 bits • High speed

4LC1M16E5

Abstract: 4C1M16E5 j13000 j130007a 1m16e 4C1M16E5-60 J1-30007-A as4c1m16e5 4lc1m16e5-60 AS4LC1M16E5
Contextual Info: H ig h P e rfo rm a n c e l M x 16 CM OS DRAM » H A S4C1M 16E5 AS4LC1M 16E5 A l M x 16 CM OS EDO DRAM Preliminary information Features • Organization: 1,048,576 words x 16 bits • High speed • 1 0 2 4 re fre sh cycles, 16 m s re fre sh in te rv a l - RAS-only or CAS-before-RAS refresh

Contextual Info: H i j j h P i - r f o r m a i K <.• L BB SV C M O S I la s h 1 I P R O M 2 A S 2 l> I ' 2 0 0 A S6K X 8/IZ8K x I6 6 K x 8 / I 2 8 K x 1 6 C M O S Jf /.isii I'I P K O M Preliminary information Features • Organization: 256KX8 or 128KX16 • Sector architecture

Contextual Info: High Perform ance lM x 16 CMOS DRAM A S4C 1M 16E 5 1 M x 16 CMOS EDO DRAM Preliminary information Features • 1024 refresh cydes, 16 ms refresh interval • Organization: 1,048,576 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh • Read-modify-write

Contextual Info: H igh p erfo rm an ce 512Kx8/256Kxl6 5V CMOS Flash EEPROM U A S 29F 400 A 512Kx8/256Kx 16 CMOS Flash EEPROM Preliminary information Features • O r g a n iz a tio n : 5 1 2 K X 8 o r 2 5 6 K X 1 6 • L o w p o w e r c o n s u m p t io n • S e c to r a r c h it e c tu r e

29F400-70

Abstract: 29f400 programming 29F400 9F400 29F400-90
Contextual Info: H ig h P erfo rm a n ce 512KX8/256KX16 5 V CMOS Flash EEPROM - A S29F400 II J ill r 5 1 2 K x 8 / 2 5 6 K x l 6 CMOS Flash EEPROM Preliminary information Features • O rganization: 5 1 2 K X 8 or 2 5 6 K x l 6 • Sector architecture - One 16K; two 8K; one 32K; and seven 64K byte sectors

AS4C256K16E0-45JC

Contextual Info: H ig h P e r fo r m a n c e 256K X 16 CM OS DRAM A S4C 256K 16E 0 A 2 5 6 K X 1 6 CM O S EDO DRAM Preliminary information Features • O r g a n iz a tio n : 2 6 2 , 1 4 4 w o r d s x 16 b its • E x te n d e d d a ta o u t • H ig h s p e e d • 5 1 2 r e f r e s h c y c le s , 8 m s r e f r e s h in te r v a l

Contextual Info: Il High Performance 256Kxl6 CMOS DRAM AS4C256K16F0 High Speed 256Kxl6 CMOS DRAM Fast Page Mode PRELIMINARY I F E A TU R E S_ • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words by 16 bits - RAS-only or CAS-before-RAS refresh

Contextual Info: Hi gh p e r f o r m a n c e 4 M b s y nc hr on ou s CMOS SRAM AS7C3256KJ6P AS7C3256K18P H '> _ 2 5 6 X X 1 6 / 18 p ip e lin e b u rst synchronous SR A M Advance information Features • O r g a n iz a tio n : 2 6 2 , 1 4 4 w o r d s

256KX16

Abstract: 64KX16 AS7C1026 AS7C3513 AS7C4098 AS7C513 cm540
Contextual Info: H igh P erform an ce 3 2 K x 16 C M O S SRAM « H AS7C513 AS7C3513 A 3 2 K x 1 6 CM OS SRAM Features • O r g a n iz a t io n : 3 2 , 7 6 8 w o r d s x 1 6 b its • H ig h s p e e d • 4 4 - p i n JEDEC s ta n d a r d p a c k a g e - 4 0 0 m i l SO J - 1 0 / 1 2 / 1 S / 2 0 n s a d d r e s s a c c e ss t im e

.5555b

Abstract: 29F200 29f200 70 ALG 2-72 29f200-90 165555H AS29F200T 6kX8 bit memory array
Contextual Info: A Hi” h IVrfnrm am r ¿ 5 6 k x 8 / I Z 8 K x 16 SV C M O S I la sh HB K IP R O M ASZ9I-200 Z ^ K x X / I 2 8 K x 1 6 C M O S ¡'l a s h I I P K O M Preliminary information Features • Organization: 256KX8 or 128KX16 • Sector architecture - O ne 16K; tw o 8K; on e 32K; and three 64K byte sectors

20014a

Abstract: 7C3256 32KX8 AS7C3256 AS7C32S6
Contextual Info: H ig h P e r f o r m a n c e 3 2 K x 8 3 .3 V C M O S SRAM . . A S7C 3256 II Jn L Low voltage 32K X 8 CMOS SRAM • TTL-com patible, three-state I /O • Ideal for cache, m odem , portable com puting - 75% p ow er reduction d uring CPU idle m ode • 2 8 -p in JEDEC standard packages