SY100S351JCTR Search Results

Contextual Info: SYN ER G Y HEX D F L I P - R OP rim 0S35i S E M IC O N D U C TO R DESCRIPTION FEATURES • Max. toggle frequency of 700MHz ■ Clock to Q max. of 1200ps ■ Ie e min. of -98mA ■ Industry standard 100K ECL levels ■ Extended supply voltage option: V ee = -4.2V to -5.5V

Contextual Info: Micrel, Inc. HEX D FLIP-FLOP FEATURES DESCRIPTION Max. toggle frequency of 700MHz Clock to Q max. of 1200ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved

F100K

Abstract: SY100S351 SY100S351JC SY100S351JCTR
Contextual Info: SY100S351 Micrel, Inc. HEX D FLIP-FLOP FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S351 DESCRIPTION Max. toggle frequency of 700MHz Clock to Q max. of 1200ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option:

F100K

Abstract: SY100S351
Contextual Info: * SYNERGY H E X D F L IP ' F L 0 P SY100S351 S E M IC O N D U C T O R _ DESCRIPTION FEATURES Max. toggle frequency of 700MHz Clock to Q max. of 1200ps min. of -98m A ESD protection of 2000V Ie e Industry standard 100K ECL levels Extended supply voltage option:

F100K

Abstract: SY100S351 SY100S351FC SY100S351JC SY100S351JCTR
Contextual Info: SY100S351 FINAL HEX D FLIP-FLOP FEATURES Q1 Q1 Q0 D0 Q0 VEES PIN CONFIGURATIONS D1 11 10 9 8 7 6 5 D2 CPa 12 13 14 15 16 17 CPb 18 D3 VEE VEES MR BLOCK DIAGRAM Top View PLCC J28-1 4 3 2 1 28 27 Q2 26 Q3 Q2 VCCA VCC VCC Q3 D Q4 R Q D4 D5 Q4 D Q Q3 E Q Q3 Q

F100K

Abstract: SY100S351 SY100S351FC SY100S351JC
Contextual Info: Micrel, Inc. SY100S351 HEX D FLIP-FLOP FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S351 DESCRIPTION Max. toggle frequency of 700MHz Clock to Q max. of 1200ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option:

F100K

Abstract: SY100S351 SY100S351FC SY100S351JC SY100S351JCTR
Contextual Info: HEX D FLIP-FLOP FEATURES The SY100S351 offers six D-type, edge-triggered, master/slave flip-flops with differential outputs, and is designed for use in high-performance ECL systems. The flip-flops are controlled by the signal from the logical OR operation on a pair of common clock signals CPa, CPb .

Contextual Info: * SYNERGY HEX D FLIP-FLOP SY100S351 SEMICONDUCTOR DESCRIPTION FEATURES Max. toggle frequency of 700MHz Clock to Q max. of 1200ps Iee min. o f-98 m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for

Contextual Info: * SYNERGY H E X D F L IP ' F L 0 P SY100S351 SEMICONDUCTOR DESCRIPTION FEATURES Max. toggle frequency of 700MHz Clock to Q max. of 1200ps Ie e min. of -98mA ESD protection of 2000V Industry standard 100K ECL levels Extended supply voltage option: Vee = -4.2V to -5.5V

F100K

Abstract: SY100S351 SY100S351JC SY100S351JCTR
Contextual Info: Micrel, Inc. HEX D FLIP-FLOP FEATURES • ■ ■ ■ ■ ■ DESCRIPTION Max. toggle frequency of 700MHz Clock to Q max. of 1200ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved