SRAM SPICE Search Results

58LC32K

Abstract: 58Lc32
Contextual Info: JÚl ft 8 19« ADVANCE MT58LC32K36C4 32K X 36 SYNCHRONOUS SRAM MICRON • SCMlCONOlATTOa MC SYNCHRONOUS SRAM 32K x 36 SRAM +3.3V SUPPLY, FULLY REGISTERED INPUTS AND OUTPUTS AND BURST COUNTER FEATURES • • • • • • • • • • • • • •

bsu 479

Abstract: atmel 912 asynchronous RAM atmel 0848 "32K x 32" SRAM 32K 4K x 8 Synchronous Dynamic RAM atmel 0529
Contextual Info: ATL25 Memory SRAMs - 1.1 - 08/00 Memory ATL25 0.25µ Compiled Gate Level SRAMs Compiled Gate Level SRAM Loading . 9-2 Common Single Port SRAM Sizes: Table. 9-2

static SRAM single port

Abstract: al5b ATMEL 910 din 74 ATL35 PRAM12X32R1W1
Contextual Info: ATL35 Memory SRAMs-1.2-04/99 Memory ATL35 0.35µ Compiled Gate Level SRAMs Compiled Gate Level SRAM Loading . 9-2 Common Single Port SRAM Sizes: Table. 9-2

Contextual Info: JUL 8 e 1993 ADVANCE MICRON • 32K celtico no üCTon Me SYNCHRONOUS SRAM MT58LC32K36B2 36 SYNCHRONOUS SRAM X 32K x 36 SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND BURST COUNTER FEATURES • • • • • • • • • • • • • • Fast access times: 9,10,12 and 17ns

FKC2

Contextual Info: ADVANCE M I lf P f lM MT58LC32K36A6 32 K x 36 SYNCHRONOUS SRAM SYNCHRONOUS SRAM 32K x 36 SRAM +3.3V SUPPLY, FULLY REGISTERED I/O AND LINEAR BURST COUNTER FEATURES • • • • • • • • • • • • • • • Fast access times: 7 ,1 0 ,1 2 and 15ns

Contextual Info: -¿UL %e ?9£3 ADVANCE MICRON I 32K KM'CONOUCTOR. MC SYNCHRONOUS SRAM X MT58LC32K36A6 36 SYNCHRONOUS SRAM 32K x 36 SRAM +3.3V SUPPLY, FULLY REGISTERED I/O AND LINEAR BURST COUNTER FEATURES • • • • • • • • • • • • • • • Fast access times: 7 ,1 0 ,1 2 and 15ns

diagram power supply LG 32 lh 35 fr

Contextual Info: JUL 8 6 NW ADVANCE MT58LC32K36M1 32K X 36 SYNCHRONOUS SRAM MICRON • SfMlCOMOlKTTOR MC 32K x 36 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND LINEAR BURST COUNTER FEATURES • • • • • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns

AN1004

Abstract: CY7C1355V25-133AC AN1003 CY7C1360V25-200AC CY7C1361V25-133AC GS84036B-100 GVT71256B36B-8 GVT71256D36T-5 MT58L256L18PT-6
Contextual Info: AN1004 APPLICATION NOTE Cycle and Access Time Interpretation for Non-Technical People SRAM vendors often differ in the way they identify a particular speed of synchronous SRAM. Synchronous SRAM speeds are identified in one of two ways, cycle time or access time also known as clock to data/output valid . This can cause confusion for those that do not understand the

80486 microprocessor block diagram and pin diagrams

Abstract: 1S1665
Contextual Info: ADVANCE iu i|i“ n f n N K 1ll1— LTc MT58LC32K36M1 32K X 36 SYNCHRONOUS SRAM SYNCHRONOUS SRAM 32K x 36 SRAM +3.3V SUPPLY W ITH CLOCKED, REGISTERED INPUTS AND LINEAR BURST COUNTER FEATURES • • • • • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns

10256K

Abstract: AMAA
Contextual Info: 32K x 36 Synchronous SRAM +3.3 V Supply With Clocked, Registered Inputs and Burst Counter FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 9,10,12, and 17 ns The Shaip Synchronous SRAM family employs high­ speed, kjw-power CMOS designs using a thin-fllm tran­

Contextual Info: PRELIMINARY 32K x 32 Pipelined Burst SRAM +3.3 V Supply, Fully Registered Inputs, Outputs, and Burst Counter FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 8 and 9 ns The Sharp Synchronous SRAM family employs high­ speed, low-power CMOS designs using a thin-film tran­

Contextual Info: 32K x 36 Synchronous SRAM +3.3 V Supply, Fully Registered Inputs, Outputs, and Burst Counter FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 7 ,10,12, and 15 ns The Sharp Synchronous SRAM family employs high­ speed, law-pcMier CMOS designs using a thm-fflm tran­

FIFO36

Abstract: DWH-11 ISERDES ML561 mig ddr virtex XAPP853 iodelay CY7C1520JV18-300BZXC K7R643684M-FC30 DWL-11
Contextual Info: Application Note: Virtex-5 Family R XAPP853 v1.2 October 6, 2008 Summary QDR II SRAM Interface for Virtex-5 Devices Author: Lakshmi Gopalakrishnan This application note describes the implementation and timing details of a Quad Data Rate (QDR II) SRAM interface for Virtex -5 devices. The synthesizable reference design leverages

FIFO36

Abstract: K7R643684M-FC30 iodelay DWL-20 ML561 XAPP853 DWH-21 ISERDES BWH-01 Virtex-5 FPGA
Contextual Info: Application Note: Virtex-5 Family R XAPP853 v1.3 June 7, 2010 Summary QDR II SRAM Interface for Virtex-5 Devices Author: Lakshmi Gopalakrishnan This application note describes the implementation and timing details of a Quad Data Rate (QDR II) SRAM interface for Virtex -5 devices. The synthesizable reference design leverages

transistor GW 93 H

Abstract: "32K x 32" SRAM
Contextual Info: LH 5 1 V 1032 C 4 PRELIMINARY 32K X 32 Pipelined Burst SRAM +3.3 V Supply, Fully Registered Inputs, Outputs, and Burst Counter FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 8 and 9 ns The Sharp Synchronous SRAM family employs high­ speed, low-power CMOS designs using a thin^ilm tran­

max 1786

Abstract: SRAM timing ATL60
Contextual Info: SRAMs-3.3-6/96 Memory ATL60 SRAMs Compiled Gate Level Compiled Gate Level SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Common Single Port SRAM Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

ATL35

Contextual Info: ATL35 Memory SRAMs-1.0-12/97 Memory ATL35 0.35µ Compiled Gate Level SRAMs Compiled Gate Level SRAMs . 9-2 Common Single Port SRAM Sizes: Table. 9-2

ATL35

Abstract: sram spice ATMEL 744
Contextual Info: ATL35 Memory SRAMs-1.0-12/97 Memory ATL35 0.35µ Compiled Gate Level SRAMs Compiled Gate Level SRAMs . 9-2 Common Single Port SRAM Sizes: Table. 9-2

ATMEL 634

Abstract: MH1099 MH1242 PO11V5 dual lvds vhdl
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

MH1099

Abstract: MH1242 PO11V5 4138G
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

ATMEL 634

Abstract: ambit rev 4 LSI CMOS GATE ARRAY PO11V5 MH1099 MH1242 705uA
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TPRAM; Gate Level or Embedded

PO88

Abstract: ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5
Contextual Info: Features • High Speed - 170 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.6 Million Used Gates and 596 pads, with 3.3V, 3V, and 2.5V libraries • System Level Integration Technology Cores on request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:

AOI222

Abstract: AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter
Contextual Info: Features • High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries • System Level Integration Technology Cores on Request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces: