SPARTAN6 Search Results

connector FMC

Abstract: connector FMC LPC samtec FMC LPC sp605 VITA-57 Samtec ASP header 12-pin VITA57 virtex-6 ML605 user guide UG537 ASP-134488-01
Contextual Info: FMC XM105 Debug Card User Guide UG537 v1.3 June 16, 2011 Copyright 2009–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

manual motherboard canada ices 003 class b

Abstract: motherboard canada ices 003 class b g31 motherboard manual motherboard canada ices 003 class a manual motherboard canada ices 003 class b user
Contextual Info: User's Guide SLLU168 – August 2012 TLK10034 Quad-Channel XAUI/10GBASE-KR Transceiver Evaluation Module EVM This user’s guide describes the usage and construction of the TLK10034 evaluation module (EVM). This document provides guidance on proper use by showing some device configurations and test modes. In

r727

Contextual Info: User's Guide SLLU180 – June 2013 TLK10232 Dual-Channel XAUI/10GBASE-KR Transceiver with Crosspoint Evaluation Module EVM Graphical Users Interface User’s Guide This user’s guide describes the usage and construction of the TLK10232 evaluation module (EVM). This

XC6LX16-CS324

Abstract: XC6SLX16 XC6LX16 carte spartan 6 xc6lx16-cs324 Xilinx Spartan6 Design Kit Spartan-6 Xilinx Ethernet development SPARTAN 6 ethernet spartan6 Spartan-6 FPGA
Contextual Info: SPARTAN-6 FPGA SP601 EVALUATION KIT ENTRY-LEVEL, LOW-COST FPGA DESIGN PLATFORM SPARTAN-6 FPGA SP601 EVALUATION KIT Accelerated Development Accelerate your Designs – Right Out of the Box • Fewer resources under tighter deadlines, new standards, and shifting requirements

Contextual Info: LogiCORE IP AXI Interconnect v1.06.a DS768 December 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI

Contextual Info: Spartan-6 FPGA Clocking Resources User Guide UG382 v1.8 June 20, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

6SLX25-2

Abstract: 3s1000-5 SPARTAN-6 image processing 3S100 DSP48A DSP48E 6SLX25 "motion jpeg" dcm verilog code
Contextual Info: Baseline ISO/IEC 10918-1 JPEG Compliance Programmable Huffman Tables two DC, two AC and JPEG-D Programmable quantization tables (four) Baseline JPEG Decoder Core Up to four color components (optionally extendable to 255 components) Supports all possible scan configurations and all JPEG formats

RAMB36E1

Abstract: RAMB16s spartan6 lx25 LX15-12 deinterlace RAM18E1 bob deinterlacer cpu 226 deinterlacer BT.656
Contextual Info: VDINT Basic BT.656 Video Deinterlacer IP Core This deinterlacer IP core converts a standard interlaced video stream to progressive video format for further processing or display. Extremely efficient, the deinterlacer core requires little area and transforms the video with practically no delay.

6SLX150-2

Abstract: verilog code for dma controller synchronous fifo design in verilog interrupt controller verilog code 6SLX150 6VCX240-2 verilog hdl code for programmable peripheral interface
Contextual Info: Full compliance with the USB 2.0 specification USBHS-DEV High Speed USB Device Controller Core The USBHS-DEV core implements a complete high/full-speed 480/12 Mbps peripheral controller that interfaces to a UTMI USB port transceiver on one side and to a system’s

verilog coding using instantiations

Abstract: DS512 XAPP917
Contextual Info: w Application Note: Migration Guide R Block Memory Generator Migration Guide XAPP917 v5.0 September 16, 2009 Summary This document provides step-by-step instructions for migrating designs containing instances of either the legacy memory cores (Dual Port Block Memory and Single Port Block Memory cores)

Contextual Info: 7 Series FPGAs Clocking Resources User Guide UG472 v1.8 August 7, 2013 The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

LPDDR KINTEX 7

Abstract: SPARTAN-6 spartan6 ug384 XA6SLX75
Contextual Info: 10 XA Spartan-6 Automotive FPGA Family Overview DS170 v1.3 December 13, 2012 Product Specification General Description The Xilinx Automotive (XA) Spartan -6 family of FPGAs provides leading system integration capabilities with the lowest total cost for highvolume automotive applications. The ten-member family delivers expanded densities ranging from 3,840 to 101,261 logic cells and faster,

UG628

Contextual Info: Spartan-6 FPGA Configuration User Guide UG380 v2.5 January 23, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

RAMB16WER

Abstract: blk_mem_gen DS512 XAPP917 vhdl coding for pipeline
Contextual Info: Application Note: Migration Guide Block Memory Generator Migration Guide XAPP917 v6.0 April 19, 2010 Summary This document provides step-by-step instructions for migrating designs containing instances of either the legacy memory cores (Dual Port Block Memory and Single Port Block Memory cores)

dcm_sp

Abstract: oserdes2 DDR spartan6 UG382 Spartan-6 FPGA DCM_CLKGEN point-to-point mini-lvds oserdes2 XAPP469 OSERDES SP601 Spread-Spectrum
Contextual Info: Application Note: Spartan-6 FPGAs Spread-Spectrum Clock Generation in Spartan-6 FPGAs XAPP1065 v1.0 March 22, 2010 Author: Jim Tatsukawa Summary Consumer display applications commonly use high-speed LVDS interfaces to transfer video data. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)

DSP48

Abstract: DSP48A DSP48E DSP48E1 PPC405 PPC440 UG112 iodelay UG440 LX240T
Contextual Info: XPower Estimator User Guide [Guide Subtitle] [optional] UG440 v4.0 May 3, 2010 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

CORDIC v4.0

Abstract: FIX16 CORDIC in xilinx CORDIC SPARTAN-3E IC BA 3812 DATASHEET CORDIC system generator xilinx cordic design for fixed angle rotation cordic design for fixed angle of rotation cordic algorithm in matlab
Contextual Info: CORDIC v4.0 DS249 April 24, 2009 Product Specification • Introduction The Xilinx LogiCORE IP CORDIC core implements a generalized coordinate rotational digital computer CORDIC algorithm. For use with Xilinx CORE Generator™ and Xilinx System Generator™ v11.1 or later.

asynchronous fifo vhdl xilinx

Abstract: vhdl synchronous bus SRL16 DS449 microblaze
Contextual Info: Fast Simplex Link FSL Bus (v2.11b) DS449 June 24, 2009 Product Specification Introduction LogiCORE Facts The FSL_V20 Fast Simplex Link (FSL) Bus is a uni-directional point-to-point communication channel bus used to perform fast communication between any

SRL16

Contextual Info: LogiCORE IP Fixed Interval Timer FIT v1.01b DS451 April 19, 2010 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP FIT core is a peripheral that generates a strobe (interrupt) signal at fixed intervals and is not attached to any bus. The Fixed Interval Timer (FIT)

PLL variable frequency generator

Abstract: QPro Virtex 4 Hi-Rel PLL 02A DS614 fpga 3 phase inverter DS6-14 MMCM
Contextual Info: Clock Generator DS614 April 19, 2010 Product Specification Introduction LogiCORE IP Facts Core Specifics The Clock Generator module provides clocks according to system wide clock requirements. Virtex -6/6CX, Spartan®-6, Spartan-3A/3A DSP, Spartan-3, Spartan-3E, Automotive

RAMB16BWER

Abstract: DSP48A1 RAMB16 RAMB16BWE INIT20 verilog code for 16 kb ram 0104220 RAMB16B
Contextual Info: Spartan-6 FPGA Block RAM Resources User Guide UG383 v1.2 February 23, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

DSP48A1

Abstract: DSP48A1 UG389 UG389 XC6SL DSP48A1 post adder XC6SLX150T verilog code for barrel shifter 8 bit carry select adder verilog code verilog code for 16 bit carry select adder systolic multiplier and adder vhdl code
Contextual Info: Spartan-6 FPGA DSP48A1 Slice User Guide [optional] UG389 v1.1 August 13, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

R_10024

Abstract: Avateq, NXP and Xilinx join to meet design challenge
Contextual Info: Avateq, NXP and Xilinx join to meet design challenge digital broadcast repeater Rev. 2 — 11 April 2012 White paper Document information Info Content Author s Alex Babakhanov – Director of Marketing, Avateq Corporation; Maury Wood – General Manager, High-Speed Converters, NXP Semiconductors

virtex 5 fpga based image processing

Abstract: DSP48A DSP48A1 DSP48E DSP48E1 Xilinx ISE Design Suite XICSI
Contextual Info: LogiCORE IP Image Characterization v1.1 DS727 September 21, 2010 Product Specification Introduction LogiCORE IP Facts Table The Xilinx Image Characterization LogiCORE IP calculates important statistical data for video input streams. The Image Characterization LogiCORE is an