DS768 Search Results

Contextual Info: LogiCORE IP AXI Interconnect v1.06.a DS768 December 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI

CS5571

Contextual Info: Errata: CS5571 - Silicon revision: B0 Reference CS5571 Data Sheet revision DS768PP1 dated March 2008. Pin 12 DITHER Logic Level vs. Pin 13 (RST) Logic Level Description The RST pin does not initialize the device correctly if pin 12 (DITHER) is held low as pin 13 (RST) is driven

DS768

Abstract: axi4-lite and apb protocol AMBA AXI to APB BUS Bridge vhdl code AXI4 lite verilog AMBA file write AXI verilog code AMBA AXI dma controller designer user guide
Contextual Info: LogiCORE IP AXI Interconnect v1.06.a DS768 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI

CS5571

Contextual Info: Errata: CS5571 - Silicon revision: AB Reference CS5571 Data Sheet revision DS768A5 dated June 2007. Analog Performance Specifications Description Currently, numerous minimum and maximum values in the Analog Characteristics table are not specified. These include Unipolar Offset After Calibration, Bipolar Offset After Calibration, Peak Harmonic or Spurious

DS768

Abstract: AMBA AXI4 verilog code axi4-lite and apb protocol AMBA AXI4 AMBA AXI to APB BUS Bridge vhdl code
Contextual Info: LogiCORE IP AXI Interconnect v1.04.a DS768 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI

AMBA AXI4 verilog code

Abstract: ZYNQ-7000 BFM 20/ZYNQ-7000 BFM
Contextual Info: LogiCORE IP AXI Bus Functional Models v3.00.a DS824 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP AXI Bus Functional Models (BFMs), developed for Xilinx by Cadence Design Systems, support the simulation of

XC7K410TFFG676-3

Abstract: XILINX ipic axi Xilinx ISE Design Suite 14.2 axi interconnect xilinx xc6vlx130t1ff ZYNQ-7000
Contextual Info: LogiCORE IP AXI Timebase Watchdog Timer axi_timebase_wdt (v1.01.a) DS763 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The Advanced eXtensible Lite (AXI) Timebase Watchdog Timer is a 32-bit peripheral that provides a 32-bit free-running timebase and watchdog timer.

axi ethernet lite software example

Abstract: zynq axi ethernet software example microblaze ethernet V101A microblaze axi ethernet lite microblaze ethernet lite
Contextual Info: LogiCORE IP Ethernet Lite MAC v1.01a DS787 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AMBA AXI Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3

d5200c

Abstract: RAMB16BWER vhdl code SECDED Xilinx ISE Design Suite 14.2 XC6SLX45T RAMB18E1
Contextual Info: LogiCORE IP AXI Block RAM BRAM Controller (v1.03a) DS777 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx Vivado™ Design Suite, Embedded Development Kit

IS61LVPS25636A

Abstract: XPS ipic axi4 example XC6SL* MEMORY state machine axi 3 protocol emc core IDT71V ise 9922 XC7K325T-FFG676
Contextual Info: LogiCORE IP AXI External Memory Controller v1.02a DS762 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The AXI External Memory Controller (EMC) IP core provides a control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular

XC6SLX16-CSG324

Abstract: XC6SLX16CSG324 uart 16550 HOLDING UART16550 16550 uart timing XC7K410TFFG676-3
Contextual Info: LogiCORE IP AXI UART 16550 v1.01a DS748 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA (Advance Microcontroller Bus Architecture) AXI (Advanced

icape2

Abstract: spartan 6 LX150 fifo generator xilinx spartan super8 circuit Spartan-6 axi crossbar
Contextual Info: LogiCORE IP AXI HWICAP v2.01.a DS817 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table This product specification describes the functionality of the Xilinx LogiCORE Intellectual Property (IP) Advanced eXtensible Interface (AXI) HWICAP

CS5571

Abstract: CS5571-ISZ LSB16 MO-150
Contextual Info: 6/25/07 14:12 CS5571 ±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ∆Σ ADC Features & Description General Description ‰ Single-ended Analog Input The CS5571 is a single-channel, 16-bit analog-to-digital converter capable of 100 kSps conversion rate. The input

AXI4 lite verilog

Abstract: AMBA AXI verilog code AMBA AXI4 verilog code AXI4 verilog AMBA AXI specifications AMBA AXI4 cdn_axi4_slave_bfm DS824 axi bfm axi wrapper
Contextual Info: AXI Bus Functional Models v2.1 DS824 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI Bus Functional Models BFMs , developed for Xilinx by Cadence Design Systems, support the simulation of customer-designed AXI-based IP. AXI

g17g2

Abstract: state machine axi 3 protocol state machine diagram for axi bridge state machine axi DS712 G17G-2 AMBA AXI specifications 17256 XILINX
Contextual Info: LogiCORE IP AXI PLBv46 Bridge v2.02.a DS712 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Advanced Microcontroller Bus Architecture (AMBA ) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI

N25Q256

Abstract: WINBOND W25Q80 XC7K325TFFG900 XC6VLX130TFF1156 W25Q64VSFIG XC7K325T W25Q64vs axi4 DS843 W25Q80
Contextual Info: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v1.00a) DS843 October 19, 2011 Product Specification Introduction LogiCORE IP Facts The AXI Quad Serial Peripheral Interface connects the AXI4 interface to SPI slave devices that support the

XC6SLX

Abstract: 2ffg1157 xps usb2 XC6SLX150
Contextual Info: LogiCORE IP AXI Universal Serial Bus 2.0 Device v3.00a DS785 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The Xilinx Universal Serial Bus 2.0 High Speed Device with an AMBA® AXI interface enables USB connectivity to a design using a minimal amount of resources. This

XC7K325TFFG900

Abstract: W25Q64VSFIG WINBOND W25Q80 SPARTAN 6 spi numonyx XPS ipic burst axi4 example Quad SPI N25Q256 NUMONYX xilinx spi XC7V285TFFG784-3 XC7K325T-ffg900
Contextual Info: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v2.00a) DS843 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad

Xilinx Spartan-6 LX4

Abstract: DS817 spartan6 jtag instruction spartan 6 LX150 fifo generator xilinx spartan state machine axi axi crossbar Xilinx Spartan 6 LX75 icape2 state machine axi 3 protocol
Contextual Info: LogiCORE IP AXI HWICAP v2.02.a DS817 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Advanced eXtensible Interface (AXI) HWICAP (Hardware Internal Configuration Access Port) core for the AXI Interface

axi interconnect xilinx

Abstract: zynq XC7Z020CLG484
Contextual Info: Zynq-7000 All Programmable SoC ZC702 Base Targeted Reference Design ISE Design Suite 14.3 User Guide UG925 (v2.1.1) November 19, 2012 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum

zynq axi ethernet software example

Abstract: microblaze, SDK axi ethernet software example MM2S Xilinx ISE Design Suite 0x10111213 axi4
Contextual Info: LogiCORE IP AXI4-Stream FIFO v2.01a DS806 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI4-Stream FIFO core allows memory mapped access to a AXI4-Stream interface. The core can be used to interface to the AXI Ethernet without the complexity

awid communication protocol

Abstract: tcl script ModelSim ISE ml605
Contextual Info: LogiCORE IP AXI Universal Serial Bus USB 2.0 Device (v3.02a) DS785 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Universal Serial Bus (USB) 2.0 High Speed Device with an Advanced Microcontroller Bus Architecture (AMBA®) Advanced

28F00AP30

Abstract: 28F00AP30TF IS61LVPS25636A XC6SL* MEMORY NUMONYX XILINX ipic axi DW10A emc core Spartan-6 FPGA
Contextual Info: LogiCORE IP AXI External Memory Controller v1.03a DS762 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI External Memory Controller EMC IP core provides a control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM

axi ethernet lite software example

Abstract: microblaze axi ethernet lite zynq axi ethernet software example microblaze ethernet lite fpga cdma by vhdl examples DS787
Contextual Info: LogiCORE IP AXI Ethernet Lite MAC v1.01.b DS787 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Advanced Microcontroller Bus Architecture (AMBA ) Advanced eXtensible Interface (AXI) AXI Ethernet Lite MAC (Media Access Controller) is