SLAVE Search Results

tsp5220

Abstract: tsp53c30 TSP50C41 tsp50c4x TSP50C30 TSP6100 53C30 wf7n TMS7000 development system TMS7000 data manual
Contextual Info: 1.0 INTRODUCTION The TSP53C30 Is a programmed TSP50C41 that operates as a slave device to a mlcroprocessor. The TSP53C30 Includes a 10 pole Linear Predictive Filter the synthesizer an 8K ROM and an 8-blt microprocessor. The speech synthesizer operates on Linear Predictive Code (LPC) or Pulse Code Modulated (PCM)

MH 7472

Abstract: ic 7472 ttl 7472 ttl TTL 7472
Contextual Info: SN5472, SN7472 AND-GATED J-K M ASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR DECEMBER 1963 - REVISED MARCH 1988 S N 5 4 7 2 . . J P AC KA G E S N 7 4 7 2 . . . N P AC K A G E Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages TO P VIE W

T 7411-1

Contextual Info: TYPES SN54111, SN74111 DUAL J-K MASTER-SLAVE FLIP-FLOPS WITH DATA LOCKOUT R E V IS E D DECEMBER 1983 S N 5 4 1 11 . . . J OR W PACKAGE • Package Options Include Plastic and Ceramic DIPs S N 7 4 1 11 . . . J OR N PACKAGE Dependable Texas Instruments Quality and

01OJ

Contextual Info: TC4027BIVBF C zM O S DIGITAL IN T E G RA T E D CIRCUIT S ILIC O N M O N OLITH IC TC4027BP/TC4027BF DUAL J-K MASTER-SLAVE FLIP-FLOP TC4027BP/BF is J-K master-slave flip-flop having RESET and SET functions. In the case of J-K made, when the clock input is given with both RESET and SET at "L", the output

SPW 12w

Abstract: TMS380c16 RRU 32
Contextual Info: TMS380C26 NETWORK COMMPROCESSOR SPW S010A -APRIL 1992- R E V IS E D MARCH 1993 I • IEEE 802.5 and IBM Token-Ring Network Compatible • Low-Cost Host-Slave I/O Interface Option • IEEE 802.3 and Blue Book Ethernet™ Network Compatible • Selectable Host System-Bus Options

Cypress VMEbus Interface Handbook

Abstract: Cypress Applications Handbook 64 pin CERAMIC QUAD FLATPACK 64-pin CERAMIC QUAD FLATPACK CY7C964-ASC G68 Package CY7C960 CY7C961 CY7C964 VIC068A
Contextual Info: 64 CY7C964 Bus Interface Logic Circuit Features • Comparators, counters, latches, and drivers minimize logic requirements for a variety of multiplexed and non-multiplexed buses • Directly drives VMEbus address and data signals • 8-bit comparator for slave address decoding

PXO 660

Abstract: DRIVER COUNTER IC 7224 IEC60747-1 J2602 SM40 SM41 SM72 SM73 UJA1023 UJA1023T
Contextual Info: UJA1023 LIN-I/O slave Rev. 04 — 5 July 2006 Product data sheet 1. General description The UJA1023 is a stand-alone Local Interconnect Network LIN I/O slave that replaces basic components commonly used in electronic control units for input and output handling.

delta plc program sample

Abstract: WM8739 WM8739EFL WM8739LEDS WM8739LEFL XWM8739EDS
Contextual Info: WM8739 / WM8739L Stereo Audio ADC DESCRIPTION FEATURES • • 90dB SNR ‘A’ weighted @ 48kHz ADC Low Power Stereo line-level audio inputs are provided, along with a mute and volume function, and master or slave mode clocking schemes. The device also has a programmable

PIC18F66J10-I/PT

Abstract: ML-ND PIC18F66J15-I/PT PIC18F4620-I/P PDF DOWNLOAD PIC18LF4620 PIC18LF4620-I/P PIC18LF4620-I/PT PIC18LF6622 PIC18LF6722-I/PT PIC18LF8722
Contextual Info: Flash Microcontrollers Cont. ds PIC18F Devices (Cont.) Memory Size Program RAM EEPROM Words Bytes Bytes 24K x 16 B 3328 1024 I/O Pins Timer/ Counters 8/16-bit UART I2C SPI™ CAN/ USB PWM A/D Analog Comp. 36 1/3 1 (EUSART) 1 (Master/ Slave) 1 ECAN 5 11-ch. 10-bit

DM54L73W

Abstract: C1995 DM54L73 DM54L73J J14A W14B
Contextual Info: DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops after a complete clock

Contextual Info: STP2021 S un M ic r o e l e c t r o n ic s J u ly 1997 PMC Power Management Controller DATA SHEET D e s c r ip t io n The STP2021 Power Management Controller brings power management to SBus-based systems. The STP2021 interfaces to the SBus via the byte-wide expansion bus EBus provided by the STP2001 Slave I/O Controller.

ci 7492

Abstract: 7492 counter TTL 7492 7492 binary counter 7492 74LSS2 ci+7492
Contextual Info: 7492, LS92 Signetics Counters Divide-By-Twelve Counter Product Specification Logic Products DESCRIPTION The '92 is a 4-bit, ripple-type Divide-by12 Counter. The device consists of four master-slave flip-flops internally con­ nected to provide a divide-by-two sec­

74LS90 pin configuration

Abstract: configuration 74ls90
Contextual Info: SPEED/PACKAGE AVAILABILITY 54 F,W S4LS F,W BLOCK DIAGRAM 54LS/74LS PIN CONFIGURATION 74 A,F 74LS A,F DESCRIPTION This monolithic counter contains four mas­ ter-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the

"dj cd"

Abstract: circuit mri oscillator
Contextual Info: * SYNERGY C o p yC lo ck m Clockworks " S E M IC O N D U C T O R FEATURES D E S C R IP T IO N Less than 500ps of edge skew between any two outputs — FOREVER Master, plus up to 3 slaves, provide up to 32 TTLcom patible outputs per board Clock frequencies to 125MHz

82077

Abstract: floppy controller 44 pin
Contextual Info: S un M icro electro nics July 1997 Slave I/O DATA SHEET Integrated SBus Interface Slave I/O Controller D e s c r ip t io n The Slave I/O Controller is a highly integrated, low-cost, low-power device designed for use in sin­ gle-processor systems with an SBus interface. The STP2001 provides serial I/O for keyboard, mouse and

UltraSPARC ii

Abstract: PI-275 UltraSPARC IIIi
Contextual Info: S un M icroelectronics July 1997 FFB DATASHEET High Performance UPA Based 24-bit Frame Buffer D e s c r ip t io n The Fast Frame Buffer FFB is a high performance UPA based 24-bit frame buffer with an integer rendering pipeline for use in demanding graphic applications. It is a UPA slave-only, non-cached, PIO graphics output

Shared resource arbitration

Contextual Info: miMHS PRELIMINARY March 1994 L 67005 DATA SHEET 8 KX 8 CMOS DUAL PORT RAM 3.3 VOLT FEATURES VERSATILE PIN SELECT FOR MASTER OR SLAVE: - M/S= H FOR BUSY OUTPUT FLAG ON MASTER - M/S = L FOR BUSY INPUT FLAG ON SLAVE INT FLAG FOR PORT TO PORT COMMUNICATION FULL HARDWARE SUPPORT OF SEMAPHORE

Contextual Info: S08 SG 8-bit Microcontrollers S08 SG Family of 8-bit Microcontrollers Enter S08 with room to grow Overview Freescale Semiconductor’s 8-bit SG family of microcontrollers MCUs is a mid to lowend offering designed for LIN slave, general market and space-constrained applications.

NJU3555

Abstract: NJU3730 NJU3730D NJU3730M do02
Contextual Info: NJU3730 PRELIMINARY 2 I C to PARALLEL CONVERTER ! PACKAGE OUTLINE ! GENERAL DESCRIPTION The NJU3730 is a serial-to-parallel converter IC, 2 which converts I C serial data into 3 bits parallel data. The NJU3730 incorporates selectable three kinds of 2 I C-slave-address, which are used to distinguish one of

Contextual Info: HD74LS390 Dual Decade Counters REJ03D0485-0400 Rev.4.00 May 10, 2006 This circuit contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters. The HD74LS390 incorporates dual divide-by-two and divide-by-five counters, which can be used to implement cycle

Contextual Info: Ordering number : ENN7672A SANYO Semiconductors DATA SHEET LC72725M LC72725V LC72725NV CMOS IC RDS Demodulation IC Overview The LC72725 is an RDS Radio Data System signal demodulation IC. This IC integrates a bandpass filter, the demodulation circuit, and buffer RAM on a single chip and can read out RDS data in slave mode operation with the

STLC2500

Abstract: bluetooth transmitter receiver parallel chip mobile mobile hardware integration integrated synthesizer vco
Contextual Info: Complete Bluetooth v1.2 feature support • Adaptive frequency hopping AFH : hopping kernel, channel assessment as master and slave Faster connections: interlaced scan for page and inquiry scan, answer FHS at first reception, RSSI used to limit range Extended SCO (eSCO) links

hcf4027be

Abstract: HCF4013B HCF4027B HCF4027BEY HCF4027BM1 HCF4027M013TR
Contextual Info: HCF4027B DUAL J-K MASTER SLAVE FLIP-FLOP • ■ ■ ■ ■ ■ ■ ■ ■ SET RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINETELY WITH CLOCK LEVEL EITHER "HIGH" OR "LOW" MEDIUM-SPEED OPERATION - 16MHz Typ. clock toggle rate at 10V

74H78

Abstract: 74LS78DC 74H54 TK27 74LS78 LS78 54H78DM 54LS78DM 74H78DC 74H78FC
Contextual Info: 78 CONNECTIO N DIAGRAMS P IN O U T A L5 4 H /7 4 H 7 8 ^ 4 L S /7 4 L S 7 8 6 / ' “ / « DUAL JK FLIP-FLOP With Common Clear and Clock and Separate Set Inputs DESCRIPTION — The 'H78 is a dual JK master/slave flip-flop with separate Direct Set inputs, a common Direct Clear input and a common Clock Pulse