SERIAL LINK INTERFACE CONTROLLER Search Results

TSB12C01A

Abstract: TSB12C01AMWNB
Contextual Info: TSB12C01AM IEEE 1394-1995 HIGH-SPEED SERIAL-BUS LINK-LAYER CONTROLLER S G L S 0 8 8 -M A R C H 1996 Link - Implements the Phy-Link Interface Described in Annex I of the IEEE 1394-1995 Serial Bus Standard Host Bus Interface - Provides Chip Control Via Directly

S2044

Abstract: D10-19 S2045
Contextual Info: PRELIMINARY DEVICE SPECIFICATION S2044/S2045 S2044/S2045 GLM COMPLIANT SERIAL INTERFACE CIRCUITS GLM COMPLIANT SERIAL INTERFACE CIRCUITS BiCMOS PECL CLOCK GENERATOR FEATURES GENERAL DESCRIPTION • Complies with the electrical and link levels of the Gigabaud Link Module GLM specification

max9265

Abstract: 0x05D3 MAX732
Contextual Info: 19-5646; Rev 0; 12/10 TION KIT EVALUA BLE IL AVA A HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface The MAX9265 gigabit multimedia serial link GMSL serializer features an LVDS system interface and high-bandwidth digital content protection (HDCP)

Contextual Info: 19-5800; Rev 0; 3/11 EVALUATION KIT AVAILABLE MAX9266 HDCP Gigabit Multimedia Serial Link Deserializer with LVDS System Interface General Description Features The MAX9266 gigabit multimedia serial link GMSL deserializer features an LVDS system interface and highbandwidth digital content protection (HDCP) decryption

Contextual Info: 19-5646; Rev 0; 12/10 TION KIT EVALUA BLE IL AVA A HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface The MAX9265 gigabit multimedia serial link GMSL serializer features an LVDS system interface and high-bandwidth digital content protection (HDCP)

CDRPLL

Abstract: MAX9266 MAX9265 3.125G prng ROSENBERGER
Contextual Info: 19-5800; Rev 0; 3/11 EVALUATION KIT AVAILABLE MAX9266 HDCP Gigabit Multimedia Serial Link Deserializer with LVDS System Interface General Description Features The MAX9266 gigabit multimedia serial link GMSL deserializer features an LVDS system interface and highbandwidth digital content protection (HDCP) decryption

lvds connector pinout

Abstract: spartan camera link LVDS connector 20 pins LCD 13.3 circuit diagram of motherboard video card MDR-26 connector vga motherboard 30 pin lvds connector 10-pin LVDS connector on display unit 14 pin vga camera pinout MOTHERBOARD pcb CIRCUIT diagram motherboard 30 pin diagram lvds
Contextual Info: Critical Link, LLC www.criticallink.com www.mitydsp.com MDK-Pro-MB MityDSP-Pro Dev. Kit Motherboard 29 September 2009 FEATURES • Standard MityDSP-Pro SO-DIMM200 Interface • RS-232 Serial Interface • USB Interface - 1.2/2.0 Compatible - 6 MBit Link Speed

DS90UR421

Abstract: DS99R124Q AEC-Q100 DS90UR241 DS99R421 RGB666 ISO106
Contextual Info: DS99R124Q 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter General Description Features The DS99R124Q converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair FPD-Link II to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial

BEADS FILTER AEC

Abstract: DS90UR421 AEC-Q100 DS90UR241 DS99R421 RGB666
Contextual Info: DS99R124AQ 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter General Description Features The DS99R124AQ converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair FPD-Link II to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial

AEC-Q100

Abstract: DS90UR241 DS99R124Q DS99R421 RGB666 DS90UR421
Contextual Info: DS99R124Q 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter General Description Features The DS99R124Q converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair FPD-Link II to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial

LVDS to MIPI CSI

Abstract: LVDS to mipi bridge MIPI csi-2 mipi csi-2 receiver mipi csi receiver MIPI D-PHY mipi csi-2 transmitter MIPI csi bridge 400x240 MIPI csi-2 receivers
Contextual Info: DS90UR910Q 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter General Description Features The DS90UR910Q is an interface bridge chip that recovers data from the FPD-Link II serial bit stream and converts into a Camera Serial Interface CSI-2 format compatible with Mobile Industry Processor Interface (MIPI) specifications. It recovers the 24- or 18-bit RGB data and 3 video sync-signals

LVDS to MIPI CSI

Abstract: mipi csi receiver DS90UH RGB mipi bridge MIPI csi bridge mipi csi-2 transmitter MIPI reference manual MIPI MIPI CSI2 interface MIPI csi-2 receivers
Contextual Info: DS90UR910Q 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter General Description Features The DS90UR910Q is an interface bridge chip that recovers data from the FPD-Link II serial bit stream and converts into a Camera Serial Interface CSI-2 format compatible with Mobile Industry Processor Interface (MIPI) specifications. It recovers the 24- or 18-bit RGB data and 3 video sync-signals

LVDS to MIPI CSI

Abstract: LVDS to mipi bridge rgb CSI2 interface RGB to CSI-2 MIPI camera interface converter RGB TO MIPI cSI2 LVDS to csi2 mipi csi receiver MIPI csi-2 receivers MIPI bridge
Contextual Info: DS90UR910Q 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter General Description Features The DS90UR910Q is an interface bridge chip that recovers data from the FPD-Link II serial bit stream and converts into a Camera Serial Interface CSI-2 format compatible with Mobile Industry Processor Interface (MIPI) specifications. It recovers the 24- or 18-bit RGB data and 3 video sync-signals

DS90UR906

Abstract: BEADS FILTER AEC DS90UR908 AEC-Q100 DS90C124 DS90UR124 DS90UR907Q DS99R124 RGB888
Contextual Info: DS90UR907Q 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter General Description Features The DS90UR907Q converts FPD-Link to FPD-Link II. It translates four LVDS data/control streams and one LVDS clock pair FPD-Link into a high-speed serialized interface (FPDLink II) over a single pair. This serial bus scheme greatly

BU19502KV

Abstract: BU19502 XTAL 25MHz ata ide 2.5 3.5 adapter hdd block diagram of DVD TQFP64 VQFP64 ata commands BU195
Contextual Info: TECHNICAL NOTE Serial ATA Interface ICs Serial ATA-IDE Bridge ICs BU19502KV 1 General BU19502 hereinafter called ‘this LSI’ is the Serial ATA to Parallel ATA Bridge LSI, in which the Physical layer, Link layer, Transport layer, Application layer of Serial ATA, and the Parallel ATA interface are all

DS90UR906

Abstract: DS99R124Q
Contextual Info: DS90UR907Q 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter General Description Features The DS90UR907Q converts FPD-Link to FPD-Link II. It translates four LVDS data/control streams and one LVDS clock pair FPD-Link into a high-speed serialized interface (FPDLink II) over a single pair. This serial bus scheme greatly

16c550

Abstract: rs485 RS485 rs232 UART windows
Contextual Info: ACQUISITION CARDS SIO-2 DATA 2 Channel Serial Communications Card The SIO-2 card allows serial communications between computers, printers, plotters, screen, PID controllers, instruments and any other device with a serial interface. 2 serial channels Link selectable RS232, RS422, RS485 or 20mA loop

RJ 45 ISO 8877

Abstract: 82521TB 82592 29025 1cdt
Contextual Info: [ p f ô iy O Ü ÏI D I M G W I n t e l' 82521TB TWISTED PAIR ETHERNET* SERIAL SUPERCOMPONENT Provides Complete Serial and Analog Twisted Pair Ethernet Interface — Analog Filters — Serial Interface and Transceiver — Manchester Encoder and Decoder — Link Integrity

LVDS to rgb888

Abstract: Ferrite Beads AEC DS90UR907Q DS90UR908 FPD-link receiver chip DS90UR906 AEC-Q100 DS90C124 DS90UR124 DS99R124
Contextual Info: DS90UR907Q April 15, 2010 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter General Description Features The DS90UR907Q converts FPD-Link to FPD-Link II. It translates four LVDS data/control streams and one LVDS clock pair FPD-Link into a high-speed serialized interface (FPDLink II) over a single pair. This serial bus scheme greatly

STC104s

Abstract: STC104
Contextual Info: Chapter ST STC101 PARALLEL DS-LINK ADAPTOR FEATURES Full duplex serial interface operating at 100 Mbits/s serial bandwidth in each direction 19 Mbytes/s bi-directional . Tx data Programmable parallel bus interface (16 and 32 bit modes). Signals Variable packet length capability.

Contextual Info: DAT A T RANSMI SS I ON High-speed Serial-bus Link-Layer Controller Provides an Easy IEEE 1394 Interface TSB12LV01A ► $ 1 1 .1 5 in q u a n tities o i l TSB12LV01AI > - $1 3 .0 0 in q u a n tities o i l TQFP PZ T he TSB12LV01A is an IEEE 1394- interface. The 1394 PHY-link interface

8 bit data link controller

Abstract: sae j1850 68HC 68HC56
Contextual Info: Order this document by BR784/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC68HC56/57 Technical Summary 8-Bit Data Link Controller Introduction The MC68HC56/57 Data Link Controller Parallel/Serial DLCP/S handles microcontroller unit (MCU) to Society of Automotive Engineers (SAE) J1850 bus interface duties. These integrated

PD10

Abstract: fxs interface integrated circuit BU7962
Contextual Info: 1/4 STRUCTURE Silicon Monolithic Integrated Circuit PRODUCTNAME BU7962GUW FUNCTION Serial Interface for Mobile Devices Application MSDL3 Mobile Shrink Data Link 3 Deserializer LSI FEATURES •Maximum transmission rate of highspeed differential interface MSDL3 is 900Mbps.

Contextual Info: 1/4 STRUCTURE Silicon Monolithic Integrated Circuit PRODUCTNAME BU7961GUW FUNCTION Serial Interface for Mobile Devices Application MSDL3 Mobile Shrink Data Link 3 Serializer LSI FEATURES •Maximum transmission rate of highspeed differential interface MSDL3 is 900Mbps.