REGISTERED BUFFER PARITY Search Results

IDT74SSTU32865

Abstract: SSTU32865
Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input

ICS98ULPA877A

Abstract: IDT74SSTUBF32866B IDTCSPUA877A Q11A
Contextual Info: DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description CONFIDENTIAL IDT74SSTUBF32866B design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

DDR3 pcb layout guidelines

Abstract: TE32882E dimm pcb layout TE32882
Contextual Info: SN74SSQE32882 www.ti.com . SCAS857A – MARCH 2008 – REVISED OCTOBER 2008 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST

SSTUB32866B

Abstract: CSPUA877 IDT74SSTUB32866B
Contextual Info: IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 1.8V CONFIGURABLE BUFFER WITH PARITY FEATURES: • • • • • • • • When used in pairs, the C0 input of the first register is tied low and the C0 input of the second register is tied high. The C1 input of both registers

ICS98ULPA877A

Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
Contextual Info: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

PI74

Abstract: PI74SSTU32866 Q13A SN74SSTU32866 SSTU32866
Contextual Info: PI74SSTU32866 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer with Parity Product Features Product Description • PI74 SSTU32866 is designed for low-voltage operation, VDD = 1.8V • Supports Low Power Standby Operation • All Inputs are SSTL_18 Compatible, except RST, C0, C1,

D8-D13

Abstract: Q11A Q13A SB866 SN74SSTUB32866 SN74SSTUB32866ZKER
Contextual Info: SN74SSTUB32866 www.ti.com SCAS792 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2

ICS97ULP877

Abstract: ICS98ULPA877A ICSSSTUB32872A IDTCSPUA877A MO-205 SSTU32864
Contextual Info: ICSSSTUB32872A Integrated Circuit Systems, Inc. Advance Information 28-Bit Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A • Optimized for DDR2 400/533/667 JEDEC 4 Rank

Contextual Info: 74SSTUB32866A www.ti.com SCAS837A – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2

J2 Q24A B

Abstract: Q24A ICS98ULPA877A ICSSSTUAF32868B IDTCSPUA877A q9bq12b
Contextual Info: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs

SSTL-15

Abstract: SN74SSTE32882 QxA11 DA11 SN74SSTE32882ZALR DDR3 pcb layout DDR3 sdram pcb layout guidelines QxA12 sstl_15 SSTL15
Contextual Info: SN74SSTE32882 www.ti.com SCAS840 – NOVEMBER 2006 28-Bit to 56-Bit Registered Buffer With Address Parity Test and One Pair to Four Pair Differential Clock PLL Driver • FEATURES • • • • • Pinout Optimizes DDR3 DIMM PCB Layout 1-to-2 Register Outputs and 1-to-4 Clock Pair

ddr3 RDIMM pinout

Abstract: EC32882S DDR3U DDR3-1866 RDIMM SPD JEDEC SSTE32882
Contextual Info: SN74SSQEC32882 SCAS920-PUB – NOVEMBER 2011 www.ti.com 28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver Check for Samples: SN74SSQEC32882 FEATURES 1 • • • • • • JEDEC SSTE32882 1-to-2 Register Outputs and 1-to-4 Clock Pair

54ACTQ827

Abstract: AM29827
Contextual Info: 54ACTQ827 Quiet Series 10-Bit Buffer/Line Driver with TRI-STATE Outputs General Description The ’ACTQ827 10-bit bus buffer provides high performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NOR output enables

upd6500

Abstract: F922 uPD65007 F981 IC tr f422 F661 CMOS GATE- NEC f422 f962 f791
Contextual Info: SEC CMOS-4L 1.5-M ICRON LOW-VOLTAGE CMOS GATE ARRAYS NEC Electronics Inc. February 1990 Description Figure 1. Sample CMOS-4L Packages NEC’s CMOS-4L family of 1.5-micron gate arrays are high-density, low-voltage application-specific integrated circuits ASICs that offer unique solutions for batterydriven circuits. Supply voltages ranging from 1.0 V to 5.5

ne 5555 timer

Abstract: "Single-Port RAM"
Contextual Info: ispLSI 6192 Cell-Based PLDs Cell-Based PLDs: The Wave of the Future! “ ” .Clearly the Next Wave of PLDs. T H IG H M I E IL T B S A Y M -S M IN RA G O R P M ER E FO M O RM R Y A P N C E Rhondalee Rohleder Pace Technologies R R LO EG G IST IC E T S

CMOS-6A

Abstract: F223 65630 F304 f422 F501 MOS l442 bt08 700201 L421 Marking
Contextual Info: NEC CM OS-6/6 A 1.0-MICRON CMOS g a t e a r r a y s NEC Electronics Inc. PRELIM INARY Description February 1990 Figure 1. Sample CMOS-6 Packages NEC’s CMOS-6 gate array families CMOS-6, CMOS6A are ultra-high performance, sub-micron channel length CM OS p ro du cts crea ted fo r h ig h -in te g ra tio n A S IC

MT36KSZF2G72LDZ

Contextual Info: 8GB, 16GB x72, ECC, QR x8 240-Pin DDR3L LRDIMM Features 1.35V DDR3L SDRAM LRDIMM MT36KSZF1G72LDZ – 8GB MT36KSZF2G72LDZ – 16GB Features Figure 1: 240-Pin LRDIMM (RC/B) MO-269 • 240-pin, load-reduced dual in-line memory module (LRDIMM) • Memory buffer (MB)

Contextual Info: Internet Data Sheet, R e v . 1 . 0 0 , M a r . 2 0 0 6 Cover Page HYS72T64000HP–[2.5F/…/3S]–B HYS72T128000HP–[2.5/…/3S]–B HYS72T128020HP–[2.5/…/3S]–B HYS72T256220HP–[2.5/…/3S]–B 240-Pin Registered DDR2 SDRAM Modules RDIM M SDRA M DDR2 SDRAM

M393B2K70DM0

Abstract: k4b4g0446d M393B5270DH0 M393B5773DH0 78FBGA M393B1K70DH0 M393B1K73DH0 M393B5273DH0
Contextual Info: Rev. 1.2, Aug. 2011 M393B5773DH0 M393B5273DH0 M393B5270DH0 M393B1K70DH0 M393B1K73DH0 M393B2K70DM0 240pin Registered DIMM based on 2Gb D-die 1.35V 78FBGA with Lead-Free & Halogen-Free RoHS compliant datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

Contextual Info: CAB4A www.ti.com SNAS630B – JULY 2013 – REVISED OCTOBER 2013 CAB4A - DDR4 Register 32-Bit 1:2 Command/Address/Control Buffer and 1:4 Differential Clock Buffer Check for Samples: CAB4A FEATURES DESCRIPTION • • • • • • • • • • • •

Contextual Info: IDT74LVC823A 3.3V CMOS ADVANCE INFORMATION 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O low-impedance loads. The device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

Contextual Info: MI CR ON S E M I C O N D U C T O R INC b7E i> L l llS H T ooossaa ^44 • MRN ADVANCE MT58LC32K36B2 32K X 36 SYNCHRONOUS SRAM M IC R O N SYNCHRONOUS SRAM 32K x 36 SRAM FEATURES • • • • • • • • • • • • • • Fast access times: 9,10,12 and 17ns

IDT74LVC828A

Abstract: LVC828A SO24-2
Contextual Info: IDT74LVC828A 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: – – – – – – – – – – IDT74LVC828A ADVANCE

IDT74LVC16827A

Abstract: LVC16827A SO56-2
Contextual Info: IDT74LVC16827A 3.3V CMOS 20-BIT BUFFER, 5 VOLT TOLERANT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: – – – – – – – – – IDT74LVC16827A Typical tSK 0 (Output Skew) < 250ps