REGISTERED BUFFER PARITY Search Results

Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32865 FEATURES: DESCRIPTION: • • • • • • • The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed

Contextual Info: IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST 1.8V CONFIGURABLE BUFFER WITH ADDRESSPARITY TEST 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer

Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input

Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input

silego

Abstract: Silego Technology DDR2-800 buffer marking code D22 q28b SILEGO q27b Q24A Q17B
Contextual Info: SLGSSTUB32868 DDR2 Configurable Registered Buffer With Parity Applications: • DDR2-800 memory modules • 28-bit, 1:2 registered buffer with parity • 1.8V data registers Features: • Supports High Density DDR2 Modules • Standard, High and Low Drive Versions

IDT74SSTU32865

Abstract: SSTU32865
Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input

silego

Abstract: Silego Technology D8-D13 D8-D25 Q11A SSTUB32866 lfbga-96ball SLGSSTUB32866B
Contextual Info: SLGSSTUB32866 DDR2 Configurable Registered Buffer With Parity Applications: • DDR2-400/533/667/800 memory modules • 1:1 25-bit or 1:2 14-bit configurable registered buffer with parity • Able to cascade with a second SLGSSTUB32866 • 1.8V data registers

D869

Contextual Info: IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 14-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32D869 FEATURES: • • • • • • • • 1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs

D869

Abstract: marking nb IDT74SSTU32D869
Contextual Info: IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 14-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32D869 FEATURES: • • • • • • • • 1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs

d869

Abstract: ef2 marking
Contextual Info: IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 14-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32D869 FEATURES: • • • • • • • • 1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs

ICS98ULPA877A

Abstract: ICSSSTUAF32866C IDTCSPUA877A
Contextual Info: DATASHEET ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

Contextual Info: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

Contextual Info: DATASHEET IDT74SSTUAE32866A 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425V to 1.575V VDD operation.

Contextual Info: DATASHEET ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: ICSSSTUAF32866B IDTCSPUA877A
Contextual Info: DATASHEET ICSSSTUAF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: ICSSSTUAF32866C IDTCSPUA877A
Contextual Info: DATASHEET ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

7120

Abstract: ICS98UAE877A IDT74SSTUAE32866A Q11A
Contextual Info: DATASHEET IDT74SSTUAE32866A 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425V to 1.575V VDD operation.

ICS98ULPA877A

Abstract: ICSSSTUAF32866B IDTCSPUA877A
Contextual Info: DATASHEET ICSSSTUAF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: IDT74SSTUBF32866B IDTCSPUA877A Q11A
Contextual Info: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: ICSSSTUAF32866C IDTCSPUA877A
Contextual Info: DATASHEET ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: IDT74SSTUBF32866B IDTCSPUA877A Q11A
Contextual Info: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

Contextual Info: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

EA32882B

Abstract: SSTE32882
Contextual Info: SN74SSQEA32882 www.ti.com. SCAS879 – JUNE 2009 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST

Contextual Info: SN74SSTEB32866 www.ti.com. SCAS851 – APRIL 2009 1.5V/1.8V 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST