SSTL_15 Search Results
SSTL_15 Result Highlights (3)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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CDCV857ADGGR |
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2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 |
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CDCV857ADGGG4 |
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2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 |
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CDCV857ADGG |
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2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 |
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SSTL_15 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 6 — 25 July 2014 Product data sheet 1. General description This 14-bit bus switch/multiplexer MUX is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS |
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CBTW28DD14 14-bit CBTW28DD14 | |
EM47DM1688SBBContextual Info: EM47DM1688SBB Revision History Revision 0.1 Jun. 2012 -First release. Jun. 2012 1/38 www.eorex.com EM47DM1688SBB 2Gb (16Mx8Bank×16) Double DATA RATE 3 SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.5V±0.075V. • All inputs and outputs are compatible with SSTL_15 |
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EM47DM1688SBB 96Ball-FBGA EM47DM1688SBB | |
EM47EM1688SBCContextual Info: EM47EM1688SBC Revision History Revision 0.1 Oct. 2014 -First release. Oct. 2014 1/37 www.eorex.com EM47EM1688SBC 4Gb (32Mx8Bank×16) Double DATA RATE 3 SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.5V±0.075V. • All inputs and outputs are compatible with SSTL_15 |
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EM47EM1688SBC 96Ball-FBGA EM47EM1688SBC | |
Contextual Info: EM47EM1688SBA Revision History Revision 0.1 Mar. 2012 -First release. Mar. 2012 1/37 www.eorex.com EM47EM1688SBA 4Gb (32Mx8Bank×16) Double DATA RATE 3 SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.5V 0.075V. • All inputs and outputs are compatible with SSTL_15 |
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EM47EM1688SBA 96Ball-FBGA | |
Contextual Info: EM47FM0888MBA 4Gb 64Mx8Bank×8 Double DATA RATE 3 low voltage SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.35V(1.283-1.45V) • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation. |
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EM47FM0888MBA 78Ball-FBGA | |
EM47FM0888SBAContextual Info: EM47FM0888SBA 4Gb 64Mx8Bank×8 Double DATA RATE 3 low voltage SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.5V±0.075V • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation. |
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EM47FM0888SBA 78Ball-FBGA EM47FM0888SBA | |
Contextual Info: PI2DDR3212 1.35V/ 1.5V/1.8V 14 bit 2:1 DDR3/DDR4 Switch Features Description ÎÎ14 bit 2:1 switch that supports DDR3 800 2133Mbps, DDR4 This 14-bit DDR3/DDR4 switch is designed for 1.35V/ 1.5V/ 1.8V supply voltage, POD_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS select input signals. It is designed for |
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PI2DDR3212 2133Mbps, 14-bit 2133Mbps PI2DDR3212 14-bit MO-220 52-Pin, PD-2102 | |
EM47FM1688MCAContextual Info: EM47FM1688MCA/SCA 8Gb 32Mx8Bank×16×2Rank Double DATA RATE 3 SDRAM Features Description • Use Two 256M x 16 dies stack to 256M x 16 x 2R DDP. • VDD/VDDQ = 1.35V -0.065/+0.1V • Backward compatible to VDD/ VDDQ = 1.5V ±0.075V. • All inputs and outputs are compatible with SSTL_15 |
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EM47FM1688MCA/SCA 96Ball-FBGA EM47FM1688MCA | |
AT0340
Abstract: RA12 fbga-96ball EM47CM1688SBA-150
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EM47CM1688SBA 96Ball-FBGA AT0340 RA12 fbga-96ball EM47CM1688SBA-150 | |
EM47FM0888MBAContextual Info: EM47FM0888MBA 4Gb 64Mx8Bank×8 Double DATA RATE 3 low voltage SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.35V(1.283-1.45V) • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation. |
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EM47FM0888MBA 78Ball-FBGA EM47FM0888MBA | |
Contextual Info: PI2DDR3212 1.35V/ 1.5V/1.8V 14 bit 2:1 DDR3/DDR4 Switch Features Description ÎÎ14 bit 2:1 switch that supports DDR3 800 2133Mbps, DDR4 This 14-bit DDR3/DDR4 switch is designed for 1.35V/ 1.5V/ 1.8V supply voltage, POD_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS select input signals. It is designed for |
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PI2DDR3212 2133Mbps, 14-bit 2133Mbps PI2DDR3212 14-bit MO-220 52-Pin, PD-2102 PI2DDR3212ZLE | |
Contextual Info: PI2DDR3212 14 bit 2:1 DDR3 Switch Features Description ÎÎ14 bit 2:1 switch that supports up to 5Gbps DDR3 signals This 14-bit DDR switch is designed for 1.5V or 1.8V supply voltage, SSTL_15 or SSTL_18 signaling and CMOS select input signals. It is designed for DDR2 or DDR3 memory bus with speed |
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PI2DDR3212 14-bit PI2DDR3212 14-bit CBTW28DD14 52-pin | |
Contextual Info: CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 4 — 12 August 2013 Product data sheet 1. General description This 14-bit bus switch/multiplexer MUX is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS |
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CBTW28DD14 14-bit CBTW28DD14 | |
EM47FM3288SBBContextual Info: EM47FM3288SBB 16Gb 64Mx8Bank×32 Double DATA RATE 3 Stack SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.5V±0.075V. • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation. • Eight Banks |
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EM47FM3288SBB 136Ball-FBGA EM47FM3288SBB | |
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Contextual Info: CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 5 — 28 May 2014 Product data sheet 1. General description This 14-bit bus switch/multiplexer MUX is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS |
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CBTW28DD14 14-bit CBTW28DD14 | |
FBGA78
Abstract: 78 ball fbga EM47EM0888SBA-150E
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EM47EM0888SBA 78Ball-FBGA FBGA78 78 ball fbga EM47EM0888SBA-150E | |
Contextual Info: EM47DM0888SBA Revision History Revision 0.1 May. 2011 -First release. May. 2011 1/39 www.eorex.com EM47DM0888SBA 1Gb (16Mx8Bank×8) Double DATA RATE 3 SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.5V 0.075V. • All inputs and outputs are compatible with SSTL_15 |
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EM47DM0888SBA 78Ball-FBGA | |
TFBGA48Contextual Info: CBTW28DD14 14-bit bus switch/multiplexer for DDR2-DDR3 applications Rev. 1 — 20 July 2010 Product data sheet 1. General description This 14-bit bus switch/multiplexer MUX is designed for 1.5 V or 1.8 V supply voltage operation, SSTL_15 or SSTL_18 signaling and CMOS select input levels. It is designed |
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CBTW28DD14 14-bit CBTW28DD14 TFBGA48 | |
Contextual Info: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EM47FM3288SBB 16Gb 64Mx8Bank×32 Double DATA RATE 3 Stack SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.5V±0.075V. • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation. |
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EM47FM3288SBB 136Ball-FBGA | |
EM47EM1688SBAContextual Info: EM47EM1688SBA Revision History Revision 0.1 Mar. 2012 -First release. Mar. 2012 1/37 www.eorex.com EM47EM1688SBA 4Gb (32Mx8Bank×16) Double DATA RATE 3 SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.5V±0.075V. • All inputs and outputs are compatible with SSTL_15 |
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EM47EM1688SBA 96Ball-FBGA EM47EM1688SBA | |
Contextual Info: TPS51916 SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011 www.ti.com Complete DDR2, DDR3 and DDR3L Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered Reference FEATURES DESCRIPTION • The TPS51916 provides a complete power supply for DDR2, DDR3 and DDR3L memory systems in the |
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TPS51916 | |
DDR4 pcb layout guidelinesContextual Info: User's Guide SLUU526 – August 2011 Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4 Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered Reference The TPS51916EVM-746 evaluation module EVM allows users to evaluate the performance of the |
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SLUU526 TPS51916EVM-746 TPS51916 TPS51916 DDR4 pcb layout guidelines | |
SSTL-15
Abstract: 204 pin so-DIMM DDR3 connector SSTL15 256Mx8 sstl_15 204Pin SODIMM ddr3 204 DDR3-1066 MODULE MEMORY DDR3 DDR3 Connector Specification
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DDR3-1066 128M/256Mx8 DDR3-1066MHz 204-pin 1066Mbps 8500MB/s SSTL-15 204 pin so-DIMM DDR3 connector SSTL15 256Mx8 sstl_15 204Pin SODIMM ddr3 204 MODULE MEMORY DDR3 DDR3 Connector Specification | |
Contextual Info: TPS51206 SLUSAH1 – MAY 2011 www.ti.com 2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For DDR2, DDR3 and DDR3L Check for Samples: TPS51206 FEATURES APPLICATIONS • • • 1 2 • • • • • • Supply Input Voltage: Supports 3.3-V Rail and |
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TPS51206 10-mA 10-pin |