REG28 Search Results

IPL30

Contextual Info: DATA SHEET Part No. AN32055A Package Code No. XBGA080-W-3737 Publication date: May 2012 Ver. AEB 1 AN32055A Contents „ Overview ……………………………………………………………………………………………………………. 3

Contextual Info: / T 7 S C S -T H O M S O N *7 M , « IM ilL Ë O T IM O S T V 0 1 1 6 PAL/NTSC DIGITAL ENCODER • BOTH 625 & 525 LINES MULTIPLEXED 8 BIT DIGITAL INPUT ACCORDING TO CCIR 601 -2 AND REC 656 ■ NTSC M, PALB, D, G, H, I, PAL N ARGEN­ TINA PROGRAMMABLE OUTPUT

QSFP DAC

Contextual Info: DS4830 Optical Microcontroller General Description Features The DS4830 provides a complete optical control, calibration, and monitor solution based on a low-power, 16-bit, microcontroller core, providing program and RAM data memory. I/O resources include a fast/accurate analog-todigital converter ADC , fast comparators with an internal

KSZ9021

Abstract: KSZ9021GQ h5007nl GMII magnetics KSZ9021gqi TLA-7T101LF GMII h5007 0010A1 KSZ90
Contextual Info: KSZ9021GQ Gigabit Ethernet Transceiver with GMII / MII Support General Description Features The KSZ9021GQ is a completely integrated triple speed • Single-chip 10/100/1000 Mbps IEEE 802.3 compliant 10Base-T/100Base-TX/1000Base-T Ethernet Physical Ethernet Transceiver

KSZ9021

Abstract: KSZ9021RL KSZ9021RLI rgmii specification h5007nl rgmii RGMII V1.3 fly back transformer monitor mlt3-to-nrzi 1000BaseT
Contextual Info: KSZ9021RL Gigabit Ethernet Transceiver with RGMII Support Data Sheet Rev. 1.0 General Description Features The KSZ9021RL is a completely integrated triple speed 10Base-T/100Base-TX/1000Base-T Ethernet Physical Layer Transceiver for transmission and reception of data

rgmii specification

Abstract: RGMII delay RGMII RGMII version 2.0 specification
Contextual Info: KSZ9021RL/RN Gigabit Ethernet Transceiver with RGMII Support Revision 1.2 General Description Features The KSZ9021RL is a completely integrated triple speed 10Base-T/100Base-TX/1000Base-T Ethernet Physical Layer Transceiver for transmission and reception of data

Contextual Info: Si5040 1 0 G b ps X F P T R A N S C E I V E R W I T H N A R R O W B A N D J I T T E R A T T E N UA T O R Features Complete, high-performance, low-power, 10 Gbps XFP transceiver featuring independent CDRs, DSPLL -based jitter-attenuating CMUs, and data retimers in both

Contextual Info: TVP70025I www.ti.com SLES232C – JUNE 2008 – REVISED APRIL 2013 TRIPLE 10-BIT, 90-MSPS, VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL Check for Samples: TVP70025I FEATURES 1 • 23 • Analog Channels – –6-dB to 6-dB Analog Gain – Analog Input Multiplexers MUXs

pin diagram of ic 3843

Abstract: IMX15 UBGA035-W-3333AEA 8361 ROM
Contextual Info: Regulations No. IC3F5472 Total Pages Page 83 1 Product Standards Part No. AN32051A Package Code No. UBGA035-W-3333AEA Semiconductor Company Panasonic Corporation Established by Applied by Checked by Prepared by M.Hiramatsu Y.Higuchi E.Sato 2009-11-18 Established

marking gb0

Abstract: SPREAD-SPECTRUM SYSTEM
Contextual Info: ICS1532 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR General Description Features The ICS1532 is a high-performance, cost-effective, 3-channel, 8-bit analog-to-digital converter with an integrated line-locked clock generator. They are part of a family of chips for high-resolution video

GND423

Abstract: PRBS31 SDD11 Si5040 Si5100 VDD432 SCK24 OTN SWITCH si5040-d
Contextual Info: Si5040 10 Gbps XFP T RANSCEIVER W I T H J I T T E R A TTENUATOR Features Complete, high-performance, low-power, 10 Gbps XFP transceiver featuring independent CDRs, DSPLL -based jitter-attenuating CMUs, and data retimers in both transmit and receive directions.

CEA-770

Abstract: SLES206A 720P50 TVP7002PZPR LCOS svga lcos 1280 1024 100-PIN TVP7002 TVP7002PZP LCOS module
Contextual Info: TVP7002 www.ti.com SLES206A – MAY 2007 – REVISED SEPTEMBER 2007 TRIPLE 8-/10-BIT 165-/110-MSPS VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL FEATURES 1 23 • Analog Channels – –6-dB to 6-dB Analog Gain – Analog Input Multiplexers MUXs – Automatic Video Clamp

10G-EPON

Contextual Info: 19-5934; Rev 1; 10/11 DS4830 Optical Microcontroller General Description The DS4830 provides a complete optical control, calibration, and monitor solution with a low-power, 16-bit, MAXQ20 microcontroller core providing generous program and RAM data memory. I/O resources include

Contextual Info: Si5040 1 0 G b ps X F P T R A N S C E I V E R W I T H N A R R O W B A N D J I T T E R A T T E N UA T O R Features Complete, high-performance, low-power, 10 Gbps XFP transceiver featuring independent CDRs, DSPLL -based jitter-attenuating CMUs, and data retimers in both

80C51

Abstract: SAA4974 frame up-conversion overlay 1998
Contextual Info: APPLICATION NOTE I²C-bus Register Specification for the SAA4974 V1.0 AN97042 Philips Semiconductors I²C-bus Register Specification for the SAA4974 V1.0 Application Note REVISION HISTORY Version Remarks 0.1 DRAFT; 18.06.97 1.0 First Release; 30.07.97 Purchase of Philips I2C components conveys a

amd RADEON igp

Abstract: RADEON IGP SB700 AMD SB700 sb710 southbridge sb700 SB7XX SB750 ite8712 2SB700
Contextual Info: AMD SB700/710/750 BIOS Developer’s Guide Technical Reference Manual Rev. 1.00 PN: 43366_sb7xx_bdg_pub_1.00 2009 Advanced Micro Devices, Inc. Trademarks AMD, the AMD Arrow logo, Athlon, and combinations thereof, ATI, ATI logo, Radeon, and CrossFire are trademarks of

Contextual Info: Doc No. TA4-EA-04511 Revision. 2 Product Standards AN32055A http://www.semicon.panasonic.co.jp/en/ 7 x 7 Dots Matrix LED Driver LSI with Step-up DC/DC Converter for White LED FEATURES DESCRIPTION • 7 x 7 LED Matrix Driver Total LED that can be driven = 49

amd SB600

Abstract: ATI SB460 SB460 ATI SB600 Athlon 64 X2 "high precision event timer" amd SB460 turion 64 x2 pin diagram amd athlon II x2 pin diagram AMD Athlon 64 X2
Contextual Info: AMD SB600 BIOS Developer’s Guide Public Version Technical Reference Manual Rev. 3.00 P/N: 46157_sb600_bdg_pub_3.00 2008 Advanced Micro Devices, Inc. Trademarks AMD, the AMD Arrow, ATI, the ATI logo, Radeon, Mobility Radeon, AMD Athlon, Sempron, Turion and

Contextual Info: r Z J S G S -T H O M S O N * l i . « G Ä iC T M D ® S T V 0 1 1 6 PAL/NTSC DIGITAL ENCODER ADVANCE DATA DESCRIPTION • BOTH 625 & 525 LINES MULTIPLEXED 8 BIT DIGITAL INPUT ACCORDING TO CCIR 601 -2 AND REC 656 ■ NTSC M, PAL B, D, G, H, I, PAL N ARGEN­

Si5338

Abstract: Si533x si5338b stk 282 STK 290 010 stk 2250 stk 282 270 BY165 si5330 data sheet AN408
Contextual Info: Si5338 I 2 C - P R O G R A M M A B LE A N Y - F R E Q U E N C Y, A N Y -O UTPU T Q U A D C L OC K G E N E R A T O R Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5     Any-frequency clock conversion

rgb to hsync vsync

Abstract: BT.709 3B335 LCOS module Hsync Vsync csync Hsync Vsync RGB Hsync Vsync separate Hsync Vsync VGA HSYNC, VSYNC counter 100-PIN
Contextual Info: TVP70025I www.ti.com . SLES232 – JUNE 2008 TRIPLE 10-BIT, 90-MSPS,

KSZ9021GQ

Abstract: KSZ9021 TLA-7T101 KSZ9021GQI Manchester CODING DECODING FPGA 0010A1 KSZ90 h5007nl
Contextual Info: KSZ9021GQ Gigabit Ethernet Transceiver with GMII / MII Support Data Sheet Rev. 1.0 General Description Features The KSZ9021GQ is a completely integrated triple speed • Single-chip 10/100/1000 Mbps IEEE 802.3 compliant 10Base-T/100Base-TX/1000Base-T Ethernet Physical

intel 82C301

Abstract: CS8232 82C301 CS8232-16 82c306 82c302 t509 t435 crystal lt 116d 83C206
Contextual Info: CH IP S £ TECHNOLOGIES INC 12E 0 | EO'ìailb 0001255 L Jj M iH i i jj i l | i l •jj»haìm •••* • alti* 8 * ,.««»} i H i r b PRELIMINARY . T-52 -33 -OS 82C 301, 82C 302, 82A 303, 82A 304, 82A 305, 82A 306 C S 8 2 3 0 : A T / 3 8 6 C H IP S e t”

Hsync Vsync VGA

Abstract: 100-PIN TVP70025IPZP TVP70025IPZPR LCOS svga lcos module 3B335
Contextual Info: TVP70025I www.ti.com . SLES232 – JUNE 2008 TRIPLE 10-BIT, 90-MSPS,