RANGE19 Search Results

Contextual Info: PRELIMINARY C Y 7C 374i UltraLogic 128-Macrocell Flash CPLD Features • • • • 128 macrocells in eight logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface • Bus Hold capabilities on all l/Os and dedicated inputs

3140ca

Contextual Info: fax id: 5220 CYPRESS CY7C008/009 CY7C018/019 PRELIMINARY 64K/128K x 8/9 Dual-Port Static RAM Features ' Fully asynchronous operation ' Automatic power-down •Expandable data bus to 16/18 bits or more using Mas­ ter/Slave chip select when using more than one device

CY82C694

Abstract: cy82
Contextual Info: PRELIM INARY CYPH CY82C694 Pentium hyperCache™ Chipset 128KB Expansion RAM Features • Interfaces directly to hyperCache™ Chipset at 66 MHz with 0 wait states » Synchronous pipelined operations with registered in­ puts and outputs • 16K x 64 common I/O architecture

CY7C1354

Abstract: CY7C1354V25 CY7C1356V25 ISIS Timing Controller
Contextual Info: CYPRESS CY7C1354V25 CY7C1356V25 PRELIMINARY 256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture Features • Pin com patible and functionally equivalent to ZBT™ • Supports 200-M Hz bus operations with zero wait states — Data is transferred on every clock

ECG book

Abstract: RETU 3.02 17313L
Contextual Info: BURR-BROüJN CORP H E D ll7 3 1 3 b S -' T | B O : " ? i - i | - 0 7 W I | 00130^ ^ — IN A 1 0 1 « • at MILITARY & DIE V E R S IO N S A V A IL A B L E lÏ Ÿ ^ W 1 '» ? Very-High Accuracy INSTRUMENTATION AMPLIFIER FEA T U R ES

Contextual Info: PRELIMINARY CY82C694 Pentium hyperCache™ Chipset 128KB Expansion RAM Features • Interfaces directly to hyperCache™ Chipset at 66 MHz with 0 wait states • Synchronous pipelined operations with registered in­ puts and outputs • 16K x 64 common I/O architecture

CY7C1355V25

Abstract: CY7C1357 CY7C1357V25
Contextual Info: CY7C1355V25 CY7C1357V25 PRELIMINARY y CYPRESS 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT™ de­ vices • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock

Contextual Info: _ RoboClockll CY7B994V C Y P R E S S PRELmNÂR¥_ CY7B993V High-Speed Multi-Phase PLL Clock Buffer Functional Description Features • 12/100-MHz (CY7B993V , or 24/185-MHz (CY7B994V) output operation • Matched pair outputs skew <200 ps • Zero input-to-output delay

Contextual Info: fax id: 5206 CY7C024/0241 CY7C025/Q251 CYPRESS 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy Functional Description Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location 4K x 16 organization CY7C024

Contextual Info: CYPRESS PRELIM INARY CY82C694 Pentium hyperCache™ Chipset 128KB Expansion RAM Features • Interfaces directly to hyperCache™ Chipset at 66 MHz with 0 wait states » Synchronous pipelined operations with registered in­ puts and outputs • 16K x 64 common I/O architecture

AOR12

Abstract: 893Q
Contextual Info: fax id: 5205 CY7C145 CY7C144 CYPRESS 8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features are included on the CY7C144/5 to handle situations when mul­ tiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for