R3306 Search Results

Contextual Info: R3306 VCXO Ultra Low Jitter 3.3V 5x7mm SMD, HCMOS/TTL Features ¾ ¾ ¾ ¾ RoHS Status <0.15ps RMS Jitter over 12KHz to 20MHz APR min ± 100ppm Start-up time is less than 5ms TRISTATE Applications ¾ ¾ ¾ Standard and High Definition Video 10 Gbit Ethernet

Contextual Info: SURFACE MOUNT R models VOLTAGE CONTROLLED CRYSTAL OSCILLATORS HCMOS/TTL 3.3V R3306, R3320, R3330 5 x 7mm Surface Mount Commercial: 0º to 70ºC TRISTATE, 3.5 MHz to 55 MHz GUARANTEED CAPTURE RANGE/ABSOLUTE PULL RANGE Guaranteed Capture Range GCR and Absolute Pull Range (APR) are terms often used interchangeably.

R3306

Contextual Info: R3306 VCXO Ultra Low Jitter 3.3V 5x7mm SMD, HCMOS/TTL Features     RoHS Status <0.15ps RMS Jitter over 12KHz to 20MHz APR min ± 100ppm Start-up time is less than 5ms TRISTATE Applications    Standard and High Definition Video 10 Gbit Ethernet

Contextual Info: R3306 VCXO Ultra Low Jitter 3.3V 5x7mm SMD, HCMOS/TTL Features ¾ ¾ ¾ ¾ RoHS Status <0.15ps RMS Jitter over 12KHz to 20MHz APR min ± 100ppm Start-up time is less than 5ms TRISTATE Applications ¾ ¾ ¾ Standard and High Definition Video 10 Gbit Ethernet

smd code marking NY

Abstract: smd transistor 712 R3320 R3330 R3306
Contextual Info: SURFACE MOUNT R models VOLTAGE CONTROLLED CRYSTAL OSCILLATORS HCMOS/TTL 3.3V R3306, R3320, R3330 5 x 7mm Surface Mount Commercial: 0º to 70ºC TRISTATE, 3.5 MHz to 55 MHz GUARANTEED CAPTURE RANGE/ABSOLUTE PULL RANGE Guaranteed Capture Range GCR and Absolute Pull Range (APR) are terms often used interchangeably.

smd code VY

Abstract: R3320 SMD MARKING CODE vx R3330 44.736 M
Contextual Info: SURFACE MOUNT VOLTAGE CONTROLLED OSCILLATORS HCMOS, 0° TO 70°C R3306, R3320, R3330 SMD Tristate 3.3V, VCXO 3 MHz to 55 MHz Surface Mount Tristate VCXOs, 3.3V These 3.3V SMD VCXOs generate an HCMOS frequency output which is controlled by the input control voltage. The end-point frequency/voltage

Contextual Info: R3306 VCXO Ultra Low Jitter 3.3V 5x7mm SMD, HCMOS/TTL Features ¾ ¾ ¾ ¾ RoHS Status <0.15ps RMS Jitter over 12KHz to 20MHz APR min ± 100ppm Start-up time is less than 5ms TRISTATE Applications ¾ ¾ ¾ Standard and High Definition Video 10 Gbit Ethernet

Contextual Info: R3306 VCXO Ultra Low Jitter 3.3V 5x7mm SMD, HCMOS/TTL Features ¾ ¾ ¾ ¾ RoHS Status <0.15ps RMS Jitter over 12KHz to 20MHz APR min ± 100ppm Start-up time is less than 5ms TRISTATE Applications ¾ ¾ ¾ Standard and High Definition Video 10 Gbit Ethernet

R3306

Contextual Info: R3306 VCXO Ultra Low Jitter 3.3V 5x7mm SMD, HCMOS/TTL Features ¾ ¾ ¾ ¾ RoHS Status <0.15ps RMS Jitter over 12KHz to 20MHz APR min ± 50ppm Start-up time is less than 5ms TRISTATE Applications ¾ ¾ ¾ Standard and High Definition Video 10 Gbit Ethernet

R3306

Abstract: VDD48
Contextual Info: R3306 VCXO Ultra Low Jitter 3.3V 5x7mm SMD, HCMOS/TTL Features     RoHS Status <0.15ps RMS Jitter over 12KHz to 20MHz APR min ± 100ppm Start-up time is less than 5ms TRISTATE Applications    Standard and High Definition Video 10 Gbit Ethernet

l9122

Abstract: IT8510 asus RC415ME 12G140001089 ATI SB600 CON3603 RC415M ISL6262CRZ foxconn
Contextual Info: 5 4 3 2 1 T12R Block Diagram FAN + SENSOR MAX6657MSA PAGE 4 V2.0 CLOCK GEN ICS951463 CPU YONAH-CM D PAGE 5 DISCHARGER CIRCUIT D PAGE 37 PAGE 2,3 Power On Sequence FSB 533MHz PAGE 40 DC/BATT IN LVDS & INV ATI RC415M PAGE 12 CRT & TV OUT PAGE 13 PAGE 41 DDR2-533

MCP67MV

Abstract: RTS5117 MCP67MV- A2 12VSUS IT8511TE D1703 D1804 D1803 asus F9DC
Contextual Info: 5 4 3 2 1 F9DC BLOCK DIAGRAM THERMAL SENSOR G781 BATTERY TYPE Page 5 D D 3S1P 3S2P FAN CTRL Page 5 AC & BAT CON Page 47 CPU S1g1 GDDR2 16Mx16 x4 DDR2 16M*16-2.5 1.8V Page42 INFINEON DDR2 SDRAM 667MHz Page2,3,4 DDR2 667 SODIMM X2 +1.8V +0.9VS Page11,12,13

r9824

Abstract: R9825 HT 1200-4 smd L9707 HT 1200-4 r9810 L9708 U5400 r2561 C3523
Contextual Info: 8 6 7 2 3 4 5 CK APPD GILA 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 1 REV ZONE ECN DATE ? ? ? EVT1 D C B PAGE PDF 1 2 3 4 6 7 8 9 10 11 13* 14 16

TAIMAG HD 081 A

Abstract: ce-0702 TAIMAG HA 003 1C-8100 ALC660 CE-0703 0845a asus sw3205 R3627
Contextual Info: 5 4 3 2 1 G1S: MEROM/965-PM/ICH8-M/NB8P-GS BLOCK DIAGRAM CLOCK GEN CK505 ICS9LPR363CGLF-T D Merom CPU FAN + THERMAL SENSOR 478B uFCPGA VRAM CH.C GDDR3 *2 LVDS PAGE 45 PAGE 46 PAGE 50 FSB 800 MHz 136 FBGA PAGE 72 NVIDIA NB8P-GS CRT PAGE 3-6 VRAM CH.A GDDR3 *2

IRF5505

Abstract: C3427 SN7002DW LD1807 343S0284 apple AirPort Extreme h11m r3361 HC17051 1n914 onsemi
Contextual Info: 6 7 B A 1 2 3 4 5 6 7 8 9 10 11 13* 14 16 17 18 21* 22 23 24 25* 26 27 28 29 30 31 32 33 34 35 36 37 38 40 44 45 46 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 REV 08/03/04 CIRCUIT

IT8511TE

Abstract: asus C5915 IT8511 C3923 J6801 c7319 R5707 T8-232 T2448
Contextual Info: 5 01 D C B A 4 Block Diagram 61 02 System Setting 62 USB CONN 03 * 63 * 04 04_CPU-Merom HOST 64 ISA ROM 05 05_CPU-Merom(PWR) 65 SPI ROM 06 * 66 LED 07 07_CRESTLINE(HOST) 67 * 08 08_CRESTLINE(DMI & CFG) 68 DC & BAT IN 09 09_CRESTLINE(GRAPHIC) 69 * 10 10_CRESTLINE(DDR2)

Attansic L1

Abstract: pr6239 RC415M RC415ME ICS951463AGLFT ASUS attansic f1 RTS5117 C3902 ICS951463
Contextual Info: 5 4 3 F5R BLOCK DIAGRAM 2 1 CPU Yonah Single core Yonah Celeron D D Page 2 AGTL+ 133/166MHz LVDS Page 10 DDR2 533/667 RC415ME CRT Single Channel PCIE Page 11 DUAL DDR2 SO-DIMM Page 12,13,14 Page 5,6,7,8,9 PCIE X4 C C MINICARD SB600 Page 28 LAN 10/100 ATTANSIC L2

C8816

Abstract: ricoh r5c833 C2335 IT8510 nvidia nb8 vga board l3404 asus CON61 R5600 D8103
Contextual Info: 5 4 3 2 1 AC_BAT_SYS 0925 +5VO 0925 + Q8200 R8209 4.7Ohm D + 1 D1_1 G1 8 2 D1_2 S1/D2_3 7 3 G2 S1/D2_2 6 4 S2 S1/D2_1 5 G D +1.05VO S Q8201 SI4800BDY @ JP8203 1 C8211 0.1UF/50V MLCC/+/-10% R8206 0Ohm C8213 4.7UF/6.3V MLCC/+/-10% 1 2 TPC28T T8209 TPC28T T8216

M51VA

Abstract: IT8512E-L C4469 U4001D asus 2sc8802 25C0401 Q3705 C4477 G780
Contextual Info: A B C D E F6Ve SCHEMATIC Revision 1.0 1 1 Content PAGE PAGE SYSTEM PAGE REF. 2 3 4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 CPU-PENRYN 1 CPU-PENRYN(2) CPU CAP, Thermal Senor

Attansic L1

Abstract: IT8511TE ALC660 bd3702 c5914 c5803 cd3102 asus attansic f1 C4422
Contextual Info: 5 Block Diagram 61 02 System Setting 62 C * 63 * 04_CPU-Merom HOST 64 ISA ROM 05 05_CPU-Merom(PWR) 65 SPI ROM * 66 07_CRESTLINE(HOST) 67 * 08 08_CRESTLINE(DMI & CFG) 68 DC & BAT IN 09 09_CRESTLINE(GRAPHIC) 69 * 10 10_CRESTLINE(DDR2) 70 Debug CONN. 11 11_CRESTLINE(PWR)

c3148

Abstract: it8511te D8802 asus 2C1208 RAY 33A A23 851-1 diode C1108 d1902 C3152
Contextual Info: A B C D E F6E SCHEMATIC Revision 1.10 1 1 Content PAGE PAGE SYSTEM PAGE REF. 2 3 4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 CPU-MEROM 1 CPU-MEROM(2) CPU CAP, Thermal Senor

it8511te

Abstract: C929B Asus VARISTOR thm MW772 ICS954310cglf d4105 U2401 IT851 ISL6262CRZ
Contextual Info: 5 4 3 2 1 TERESA Block Diagram FAN + SENSOR ADM1032ARMZ PAGE 4 CLOCK GEN ICS954310 CPU D D T2060 4xx,5xx Series PAGE 5 DISCHARGER CIRCUIT PAGE 2,3 PAGE 37 FSB 533MHz Power On Sequence PAGE 40 DC/BATT IN GMCH-M Calistoga 943GML B0:02G010009121 LVDS & INV PAGE 12

c2315

Abstract: IC401B C2068 R1962 asus mcp 430 nvidia C1567 PJP5403 C2061 C51MV MCP51
Contextual Info: A B C D E T13M SCHEMATIC Revision 1.1 Content PAGE 2 3 4 5 PAGE SYSTEM PAGE REF. 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 AMD S1 CPU 1 -HT&MISC AMD S1 CPU(2)-DDRII

APPLE A6 CHIP

Abstract: cf325 W07 sot 23 C-492-5 SMD M05 sot23 C4977 cf406 p66 apple c5297 I342
Contextual Info: 8 6 7 PDF CSA CONTENTS IMG5 17" REV E 11/01/05 SYNC MASTER DATE PDF CSA CONTENTS TABLE_TABLEOFCONTENTS_HEAD 2 System Block Diagram FINO-DD 06/20/2005 TABLE_TABLEOFCONTENTS_ITEM 3 4 Power Block Diagram FINO-PC 06/20/2005 5 Table Items FINO-M23 08/26/2005 6