PROGRAMMABLE STATE MACHINE Search Results

Contextual Info: COM’L Advanced Micro Devices PLS30S16-40 28-Pin Universal Programmable Logic Sequencer DISTINCTIVE CHARACTERISTICS • Field-programmable replacement for sequential logic - Eases design and speeds time to market ■ Advanced Mealy state machine architecture

AN050

Abstract: PLUS405
Contextual Info: Philips Semiconductors Programmable Logic Products Application Note Implementing Counters in Sequencer Devices INTRODUCTION Some state machine applications require a state machine to wait for a number of clock pulses to occur before some decision point is

RLink jtag pinout

Contextual Info: STLUX385A Digital controller for lighting and power conversion applications with 6 programmable PWM generators, 96 MHz PLL, DALI Datasheet - production data TSSOP38 Features • 6 programmable PWM generators SMEDs (state machine event driven) – 10 ns event detection and reaction

Contextual Info: STLUX385A Digital controller for lighting and power conversion applications with 6 programmable PWM generators, 96 MHz PLL, DALI Datasheet - production data TSSOP38 Features • 6 programmable PWM generators SMEDs (state machine event driven) – 10 ns event detection and reaction

Monolithic Memories PROM programming

Abstract: 14r21 type KX4 MONOLITHIC MEMORIES PROM A1643 d1641 PMS14R21 Monolithic Memories
Contextual Info: M onolithic G P M S 1 4 R 2 1 /A Programmable Sequencer PROSE Family l M e m o ries Patent Pending / / / ////////////////////////////////////////Æ A D V A N C E INFORMATION Features/ Benefits Description • User-programmable synchronous state machine

AN032

Abstract: 74F50729 74F50109 74F50728 74F5074 74F74 AN219 5 pin AN032
Contextual Info: Philips Semiconductors Programmable Logic Devices Application Note Minimize metastability in 50MHz state machines Engineers are excited to discover the PLUS405–55, a PLD state machine IC rated for a maximum operating frequency of 55MHz. It has a flexible architecture offering

B272

Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

B272

Abstract: 149-IO
Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

3192-70LQI

Abstract: B272
Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

memoria rom y ram

Abstract: FA 5323
Contextual Info: PROSE PMS14R21 /A Programmable Sequencer Ordering Information Features/ Benefits • User-programmable synchronous state machine • 30 MHz maximum internal frequency, 25 MHz external • Allows up to 128 states or complex designs • 8 inputs and 8 outputs with 13 buried feedback signals

CY7C330

Contextual Info: fax id: 6019 1CY 7C33 0 CY7C330 CMOS Programmable Synchronous State Machine • 66-MHz operation — 3-ns input set-up and 12-ns clock to output Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — 15-ns input register clock to state register clock

AM29PL141

Abstract: 29PL141 Am29100
Contextual Info: Am29PL141 A m 29PL141 Fuse Programmable Controller FPC ADVANCED INFORMATION DISTINCTIVE CHARACTERISTICS Implements complex fuse programmable state ma­ chines 64 words of 32-bit-wide microprogram memory Serial Shadow Register (SSRaTM>) Hio diagnostics on chip

gmoc

Abstract: Am29PL141
Contextual Info: Am29PL141 Am29PL141 Fuse Programmable Controller FPC DISTINCTIVE CHARACTERISTICS Implements complex fuse programmable state ma­ chines 7 conditional inputs, 16 outputs 64 words of 32-bit-wide microprogram memory q TM>) diagnostics Hionn Serial Shadow Register (SSR

Contextual Info: TIB82S167BC 14 x 48 x 6 FIELD-PROGRAMMABLE LOGIC SEQUENCER WITH 3-STATE OUTPUTS OR PRESET _ SRPS026- D2896, JANUARY 1985- REVISED MARCH 1992 NT PACKAGE TOP VIEW Programmable Asynchronous Preset or Output Control Power-On Preset of All Flip-Flops

Contextual Info: Lattice' ispLSr 3192 | Semiconductor I Corporation High Density Programmable Logic Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: Lattica ispLSI 3256A ;Semiconductor I Corporation High Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 1281/0 Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: Lattice' ispLSI 3320 | Semiconductor I Corporation Features High-Density Programmable Logic Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 160 I/O Pins — 14000 PLD Gates — 480 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: ® ispLSI and pLSI 2096 High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC 4000 PLD Gates 96 I/O Pins, Six Dedicated Inputs 96 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State

Contextual Info: Lattice' ispLSI 3320 | Semiconductor I Corporation Features High-Density Programmable Logic Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 160 I/O Pins — 14000 PLD Gates — 480 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: Lattica ispLSI 3192 ;Semiconductor I Corporation High Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

1048C

Abstract: 1048E
Contextual Info: ispLSI 1048E High-Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State

Contextual Info: ispLSI 2096V 3.3V High Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

1048E

Abstract: 1048E-50 0127A 1048C
Contextual Info: ispLSI 1048E In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State

ISP1016

Abstract: 1016-60 lattice 1016-60LJ Lattice 1016-80LJ 1016E 1016-60LH
Contextual Info: ispLSI 1016 In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — Wide Input Gating for Fast Counters, State