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| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
7c361Contextual Info: M CY7C361 CYPRESS SEMICONDUCTOR Features • High speed: 125-MHz state machine output generation — Token passing — M ultiple, concurrent processes — Multiway branch or join Ultra High Speed State Machine EPLD — Skew-controlled OR output array — Outputs are sum o f states like PLA |
OCR Scan |
cy7c36128-pin300-m361--83hc+3 | |
CY7C361Contextual Info: CY7C361 PRELIMINARY s CYPRESS SEMICONDUCTOR A programmable on-board clock doubler allows the device to operate at 125 MHz in ternally based on a 62.5-MHz input clock reference. The clock doubler is not a phase-lockedloop. It produces an internal pulse on each edge of the external clock. |
OCR Scan |
cy7c361125-mhz10-year28-pin+1 | |
CY7C361Contextual Info: CY7C361 CYPRESS SEMICONDUCTOR The CY7C361 is a CMOS erasable, pro grammable logic device EPLD with very high speed sequencing capabilities. A programmable on-board clock doubler allows the device to operate at 125 MHz in ternally based on a 62.5-MHz input clock |
OCR Scan |
cy7c361125-mhz28-lead300-mil+1 | |
CY7C361
Abstract: c3611 one hot state machine Cypress Applications Handbook 7C361 83HM
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cy7c361125-mhz10-year28-pin+8 |