POSTED CAS JEDEC Search Results

W3H32M72E-XSBX

Abstract: calibration definition
Contextual Info: White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Programmable CAS latency: 3, 4, 5, or 6 Package: Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

W3H64M72E-XSBX

Contextual Info: White Electronic Designs W3H64M72E-XSBX ADVANCED* 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Programmable CAS latency: 3, 4 or 5 Package: Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 17 x 23mm

Contextual Info: White Electronic Designs W3H64M72E-XSBX 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4 or 5 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 16 x 22mm

Contextual Info: White Electronic Designs W3H64M72E-XSBX ADVANCED* 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667*, 533, 400 „ Programmable CAS latency: 3, 4 or 5 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 17 x 23mm

Contextual Info: White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4, 5, or 6 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

W3H32M72E

Abstract: BA0BA12
Contextual Info: White Electronic Designs W3H32M72E-XSBX 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES  Data rate = 667, 533, 400  Programmable CAS latency: 3, 4, 5, or 6  Package:  Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

Contextual Info: White Electronic Designs W3H64M72E-XSBX PRELIMINARY* 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667*, 533, 400 „ Programmable CAS latency: 3, 4 or 5 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 16 x 22mm

W3H32M72E

Contextual Info: White Electronic Designs W3H32M72E-XSB2X Preliminary 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES  Data rate = 667, 533, 400  Programmable CAS latency: 3, 4, 5, or 6  Package:  Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 16 x 20mm

Contextual Info: White Electronic Designs W3H32M72E-XSBX * 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4, 5, or 6 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

Contextual Info: White Electronic Designs W3H64M72E-XSBX ADVANCED* 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667*, 533, 400 „ Programmable CAS latency: 3, 4 or 5 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 16 x 22mm

Contextual Info: White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4, 5, or 6 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

W3H128M72ER-XSBX

Abstract: M2 8gb pinout
Contextual Info: White Electronic Designs W3H128M72ER-XSBX PRELIMINARY* 128M x 72 REGISTERED DDR2 SDRAM 255 PBGA FEATURES „ Data rate = 667, 533, 400 Mb/s „ Posted CAS additive latency: 0, 1, 2, 3 or 4 „ Package: „ Write latency = Read latency - 1* tCK „ Commercial, Industrial and Military Temperature

W3H128M72ER-XSBX

Abstract: LDM-1 W3H128M72
Contextual Info: White Electronic Designs W3H128M72ER-XNBX PRELIMINARY* 128M x 72 REGISTERED DDR2 SDRAM 255 PBGA FEATURES  Data rate = 667, 533, 400 Mb/s  Posted CAS additive latency: 0, 1, 2, 3 or 4  Package:  Write latency = Read latency - 1* tCK  Commercial, Industrial and Military Temperature

icc20

Contextual Info: White Electronic Designs W3H128M64E-XSBX ADVANCED* 128M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 Mb/s „ Posted CAS additive latency: 0, 1, 2, 3 or 4 „ Package: „ Write latency = Read latency - 1* tCK • 208 Plastic Ball Grid Array PBGA , 16 x 22mm

W3H128M72ER-XSBX

Abstract: 74sstu32864
Contextual Info: White Electronic Designs W3H128M72ER-XSBX ADVANCED* 128M x 72 REGISTERED DDR2 SDRAM 255 PBGA FEATURES „ Data rate = 667, 533, 400 „ Package: „ CK/CK# Termination options available • 0 ohm, 20 ohm • 255 Plastic Ball Grid Array PBGA , 22 x 26mm „ Posted CAS additive latency: 0, 1, 2, 3 or 4

Contextual Info: White Electronic Designs W3H128M72E-XNBX ADVANCED* 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 Mb/s „ Posted CAS additive latency: 0, 1, 2, 3 or 4 „ Package: „ Write latency = Read latency - 1* tCK • 208 Plastic Ball Grid Array PBGA , 16 x 22mm

W3H128M72E-XSBX

Contextual Info: White Electronic Designs W3H128M72E-XSBX 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Package: „ CK/CK# Termination options available • 0 ohm, 20 ohm • 208 Plastic Ball Grid Array PBGA , 16 x 22mm „ Posted CAS additive latency: 0, 1, 2, 3 or 4

W3H128M72E-XSBX

Abstract: 84 FBGA
Contextual Info: White Electronic Designs W3H128M72E-XSBX 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES  Data rate = 667, 533, 400  Package:  CK/CK# Termination options available • 0 ohm, 20 ohm • 208 Plastic Ball Grid Array PBGA , 16 x 22mm  Posted CAS additive latency: 0, 1, 2, 3 or 4

Contextual Info: ESM T M14D1G1664A 2D 7DDR II SDRAM 8M x 16 Bit x 8 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

M14D5121632A

Abstract: M14D512
Contextual Info: ESMT Preliminary M14D5121632A (2T) DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

Contextual Info: ESM T M14D2561616A 2L (Preliminary) DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

M14D256

Contextual Info: ESMT Preliminary M14D2561616A (2L) DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

Contextual Info: ESM T M14D128168A 2M DDR II SDRAM 2M x 16 Bit x 4 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

M14D1G166

Abstract: m14d1g M14D1G1664A m14d1g16 DDRII esmt
Contextual Info: ESMT M14D1G1664A 2D 7DDR II SDRAM 8M x 16 Bit x 8 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.