74SSTU32864 Search Results

A115-A

Abstract: C101
Contextual Info: 74SSTU32864CZKERĆJ 25ĆBIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES621 − DECEMBER 2004 D Member of the Texas Instruments D D D D D D D Supports LVCMOS Switching Levels on the Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout

Contextual Info: 74SSTU32864CZKERĆJ 25ĆBIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES621 − DECEMBER 2004 D Member of the Texas Instruments D D D D D D D Supports LVCMOS Switching Levels on the Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout

Contextual Info: 74SSTU32864CZKERĆJ 25ĆBIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES621 − DECEMBER 2004 D Member of the Texas Instruments D D D D D D D Supports LVCMOS Switching Levels on the Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout

MT 5388 BGA

Abstract: Broadcom 7019 BTS 6000 ericsson alcatel 1511 mux mobile switching center msc ericsson bts 6000 2x4 TTL demultiplexer cisco 2801 ericsson bts Technical specification alcatel 1511
Contextual Info: IDT Product Selector Guide Accelerated Thinking SM Table of Contents Integrated Processors Flow-Control Management Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

W3H128M72ER-XSBX

Abstract: 74sstu32864
Contextual Info: White Electronic Designs W3H128M72ER-XSBX ADVANCED* 128M x 72 REGISTERED DDR2 SDRAM 255 PBGA FEATURES „ Data rate = 667, 533, 400 „ Package: „ CK/CK# Termination options available • 0 ohm, 20 ohm • 255 Plastic Ball Grid Array PBGA , 22 x 26mm „ Posted CAS additive latency: 0, 1, 2, 3 or 4