PIPELINING Search Results

80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Contextual Info: SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  Two Instructions Clock Sustained Execution  Four 59 Mbytes s DMA Channels with Data Chaining  Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions clock Execution

IDT49C410

Abstract: IDT49C402 IDT49C818
Contextual Info: FAST CMOS OCTAL REGISTER W ITH SPC Serial P r o t o c o l C h a n n e l ADVANCE INFORMATION IDT49C818 Inu'-v«1 DESCRIPTION: FEATURES: • High-speed non-inverting 8-bit parallel register for any data path, control path or pipelining application • Pin-out similar to the Am29818 and 54/74S818, but uses an

008 cow 734

Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining

Contextual Info: 80960CF-40 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining

L39c

Abstract: IDT49C403 signal path designer
Contextual Info: HIGH SPEED 16-BIT REGISTER WITH SPC ^IDT49FCT618 ?49FC T618A id FEATURES: DESCRIPTION: • High-speed non-inverting 16-bit parallel data register for any data path, control path or pipelining application • Read back path from the data output back to the data input

270710

Abstract: CX041A
Contextual Info: ^ 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR * Two Instructions/Clock Sustained Execution * Four 59 Mbytes/s DMA Channels with Data Chaining * Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

29c818

Abstract: AN29C
Contextual Info: Am29C818A Advanced Micro Devices CMOS Pipeline Register with SSR Diagnostics DISTINCTIVE CHARACTERISTICS • ■ High-speed noninvertirg 8-bit parallel register for any data path o r pipelining application ■ WCS W ritable Control store pipeline register

AM90C256-12

Abstract: Am90C256-08 AM90C256-10
Contextual Info: Am90C256 256K x 1 CM O S Enhanced Page Mode Dynamic RAM PRELIMINARY 9SZ006UJV DISTINCTIVE CHARACTERISTICS • • • • • C ontinuous data rate over 25 MHz Random access within a row Flow-through colum n latch fo r pipelining Low operating current - 70 mA

GVT71256B36TA-7

Abstract: GVT71256B36T-7 CY7C1361A-100AI
Contextual Info: 361A CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Flowthrough Burst SRAM Features • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip

Contextual Info: CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

for full adder and half adder

Abstract: datasheet for full adder and half adder carry save adder 16-bit adder pasic380 half adder transistor h9 16 bit adder 16 bit full adder applications of half adder
Contextual Info: DESIGN TIPS Carry-Save Addition Saves Logic, Time Summing multiple operands is a common operation for signal processing applications. One such application requires summing eight, 16-bit operands to generate a 19-bit result. Pipelining is required to achieve the system’s required

parametric equalizer ic

Abstract: 24 bits usb audio interface UAC 3556B UAC3553B AUDIO headphone amplifier digital bass control 3553B 3556B parametric equalizer UAC 3555B UAC355xB
Contextual Info: PRODUCT INFORMATION UAC 3553B March/2004 UAC 3553B USB Audio DAC The UAC 3553B is a fully integrated 2-channel audio digital-to-analog converter DAC with an integrated USB 2.0 full-speed interface controller. remote-controlled via I2C slave operation. This allows communication pipelining

631J

Abstract: 74AS818 49FCT818 CY-320 IDT49C403
Contextual Info: HIGH-SPEED OCTAL REGISTER WITH SPC In tegrated D evice T ech n o lo gy, Inc. FEATURES: • • • • • • • • • High-speed, non-inverting 8 bit parallel register fo r any data path, control path or pipelining application New, unique comm and capability which allows for

SSR 80 DA

Abstract: am di he ne
Contextual Info: Am29818A Pipeline Register wi h SSR Diagnostics Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • High-speed noninvertln£ 8-bit parallel register for any data path or pipelining application ■ WCS W ritable Control S tore pipeline register ■

SAMPLE HOLD

Abstract: CY7C1440V33
Contextual Info: 440V33 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY 1M x 36 / 2M x 18 / 512K x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • inputs include all addresses, all data inputs, address-pipelining Chip Enable CE , burst control inputs (ADSC, ADSP, and

Contextual Info: 1CY7C1329 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

CY7C1382

Contextual Info: CY7C1380A CY7C1382A PRELIMINARY 512K x 36 / 1M x 18 Pipelined SRAM Features inputs, address-pipelining Chip Enable CE , burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd and BWE), and Global Write (GW). • • • • • •

Contextual Info: PRELIMINARY CY7C1344A/GVT7164B36 64K x 36 Synchronous Burst SRAM Features • • • • • • • • • • • • • • • • The CY7C1344A/GVT7164B36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip

Contextual Info: w 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining 32-bit Parallel Architecture — Two Instructions/clock Execution

Contextual Info: iny SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 M bytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture

NT55

Abstract: AM29C818A CD3024 PD3024 AM29C818APC
Contextual Info: Advanced Micro Devices A m 2 9 C 8 1 8 A CMOS Pipeline Register with SSR Diagnostics DISTINCTIVE CHARACTERISTICS • ■ High-speed noninverting 8-bit parallel register for any data path or pipelining application WCS Writable Control Store pipeline register

CY7C1381B

Abstract: CY7C1381BV25 CY7C1383B CY7C1383BV25
Contextual Info: CY7C1381BV25 CY7C1383BV25 PRELIMINARY 512K x 36 / 1M x 18 Flow-Thru SRAM Features controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), Burst Control Inputs

Contextual Info: 327A CY7C1327A/GVT71256G18 256K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • eral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

GVT71256B36T-7

Abstract: CY7C1363A GVT71256B36 GVT71512B18 926B1 a453t GVT71256B36TA
Contextual Info: 1CY7C1361A CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip