CY7C1382 Search Results

CY7C1382DV33-200BZI

Contextual Info: CY7C1380DV33 CY7C1382DV33 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades is 200 MHz ■ Registered inputs and outputs for pipelined operation

CY7C1380BV25

Abstract: CY7C1382BV25
Contextual Info: 1CY7C1380BV25 CY7C1380BV25 CY7C1382BV25 PRELIMINARY 512K x 36 / 1 Mb x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 200,166, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns

1382C

Contextual Info: 380C CY7C1380C CY7C1382C PRELIMINARY 512K x 36 / 1M x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns

Contextual Info: CY7C1380D CY7C1382D PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

1382C

Contextual Info: CY7C1380C CY7C1382C 512K x 36/1M x 18 Pipelined SRAM Features Functional Description • Fast clock speed: 250, 225, 200, 167, 133 MHz • Provide high-performance 3-1-1-1 access rate • Fast OE access times: 2.6, 2.8, 3.0, 3.4, 4.2ns • Optimal for depth expansion

CY7C1380DV25

Abstract: CY7C1382DV25
Contextual Info: CY7C1380DV25 CY7C1382DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1380D CY7C1380F CY7C1382D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation

CY7C1380B-133AC

Abstract: CY7C1380B CY7C1382 CY7C1382B
Contextual Info: 380B CY7C1380B CY7C1382B 512K x 36/1M x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 200, 167, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns Optimal for depth expansion

CY7C1382

Contextual Info: CY7C1380A CY7C1382A PRELIMINARY 512K x 36 / 1M x 18 Pipelined SRAM Features inputs, address-pipelining Chip Enable CE , burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd and BWE), and Global Write (GW). • • • • • •

Contextual Info: CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description The CY7C1380D/CY7C1380F/CY7C1382D/CY7C1382F[1] SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells

Contextual Info: CY7C1380D CY7C1382D 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply

Contextual Info: CY7C1380DV25 CY7C1382DV25 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation • 2.5V core power supply

CY7C1380CV25

Abstract: CY7C1382CV25 1382C
Contextual Info: 380CV25 CY7C1380CV25 CY7C1382CV25 PRELIMINARY 512K x 36/1M x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns

AN1064

Abstract: CY7C1380D CY7C1380F CY7C1382D CY7C1382F INTEL-PENTIUM 32D10
Contextual Info: CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Features Functional Description The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F[1] SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit

CY7C1380CV25

Abstract: CY7C1380CV25-250AC CY7C1382CV25
Contextual Info: CY7C1380CV25 CY7C1382CV25 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200,166 and 133 MHz • Registered inputs and outputs for pipelined operation

CY7C1380B

Abstract: CY7C1382 CY7C1382B
Contextual Info: 1CY7C1380B CY7C1380B CY7C1382B PRELIMINARY 512K x 36 / 1 Mb x 18 Pipelined SRAM Features inputs, address-pipelining Chip Enable CE , burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd and BWE), and Global Write (GW). • • •

Contextual Info: CY7C1380DV33 CY7C1382DV33 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades is 200 MHz ■ Registered inputs and outputs for pipelined operation

CY7C1380BV25-167AC

Abstract: CY7C1380BV25 CY7C1380BV25-200AC CY7C1382BV25 CY7C1380BV25-167BZC
Contextual Info: CY7C1380BV25 CY7C1382BV25 512K x 36 / 1M x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 200,167, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0, 3.4, 3.8, 4.2 ns Optimal for depth expansion

CY7C1380D

Abstract: CY7C1382D
Contextual Info: CY7C1380D CY7C1382D PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200 and 167 MHz Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1380DV25 CY7C1382DV25 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation • 2.5V core power supply

Contextual Info: CY7C1380DV25 CY7C1382DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200,167, and 133 MHz • Registered inputs and outputs for pipelined operation

AN1064

Abstract: CY7C1380D CY7C1380F CY7C1382D CY7C1382F
Contextual Info: CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F[1] SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells

Contextual Info: 380CV25 CY7C1380CV25 CY7C1382CV25 PRELIMINARY 512K x 36/1M x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns