PIPELINE Search Results

Contextual Info: TOSHIBA TC55V2325FF-100 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 65,536 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V2325FF is a 2 ,0 9 7 ,1 5 2 bit synchronous pipelined burst SRAM that is organized as 65,536 words by 32 bits and designed for use in a secondary cache to support MPUs which have burst

UM61L3232AF-7

Abstract: UM61L3232A um61 UM61L UM61L3232 UM61L3232AF-8 UM61-l-3232af
Contextual Info: UM61L3232A Series PRELIMINARY 32K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Features Fast access times: 5/6/7/8 ns Single +3.3V+10% or +3.3V-5% power supply Synchronous burst function Individual Byte W rite control and Global Write

Contextual Info: ADS809 ADS 809 www.ti.com 12-Bit, 80MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES DESCRIPTION ● DYNAMIC RANGE: SNR: 65dB at 10MHz fIN SFDR: 68dB at 10MHz fIN The ADS809 is a high-dynamic range 12-bit, 80MHz pipelined Analog-to-Digital A/D converter. It includes a

Contextual Info: Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY29FCT520T Multi-Level Pipeline Register SCCS011 - May 1994 - Revised February 2000 Features Functional Description • Function, pinout, and drive compatible with FCT, F

diode p4e

Contextual Info: TLC34058 256 x 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 • • • • • • • • LinEPIC 1-µm CMOS Process 125-MHz Pipelined Architecture Available Clock Rates . . . 80, 110, 125, 135 MHz Dual-Port Color RAM 256 Words x 24 Bits Bit Plane Read and Blink Masks

AxC11

Contextual Info: N EC ELECTRONICS INC dEEC ^ t 7 E 1 • tMS7S2S DG3R58b MM3 H N E C E _ 16Mbit Synchronous DRAM_ CONTENTS Programable 3 - stage pipeline. Features.

CQFP352

Abstract: QFP352 MCGA349 MCGA-349 adc controller vhdl code atmel 268 AT7913 CQFP352 package vhdl code 64 bit FPU SPARC v8 architecture BLOCK DIAGRAM
Contextual Info: ATMEL AT7913E SpaceWire Remote Terminal Controller RTC DATASHEET Features • LEON2-FT Sparc V8 Processor • • • • • • • • • • • 5 stage pipeline 4K instruction caches / 4K data caches Meiko FPU Interrupt Controller Uart serial links

Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state

Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

ADS5221

Abstract: ADS5221PFBR ADS5221PFBT OPA695 QFN-48 THS4503 TQFP-48
Contextual Info: ADS5221 ADS 522 1 SBAS262C – APRIL 2003 – REVISED JUNE 2007 12-Bit, 65MSPS Sampling, +3.3V ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● The ADS5221 is a pipeline, CMOS Analog-to-Digital Converter ADC that operates from a single +3.3V power

MS-026

Abstract: MT55L256L32P MT55L256L36P MT55L256V32P MT55L256V36P MT55L512L18P MT55L512V18P
Contextual Info: 8Mb: 512K x 18, 256K x 32/36 PIPELINED ZBT SRAM 8Mb ZBT SRAM MT55L512L18P, MT55L512V18P, MT55L256L32P, MT55L256V32P, MT55L256L36P, MT55L256V36P 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • • • • • • •

AS7C331MNTD32A

Abstract: AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A
Contextual Info: November 2004 AS7C331MNTD32A AS7C331MNTD36A 3.3V 1M x 32/36 Pipelined SRAM with NTDTM Features • Organization: 1,048,576 words × 32 or 36 bits • NTD architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns

A65H73361

Abstract: A65H83181 SA10 SA11 SA12 SA13 SA15
Contextual Info: A65H73361/A65H83181 Series 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Preliminary Document Title 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Revision History Rev. No. 2.0 PRELIMINARY

low input capacitance buffer

Abstract: A112 A113 WM2331 electrolytic capacitor, .1uF 50v
Contextual Info: WM2331 10-bit 30MSPS ADC with PGA and Clamp DESCRIPTION FEATURES The WM2331 is a high speed, 10-bit pipeline analogue-todigital converter ADC with on-chip programmable gain amplifier (PGA) and clamp circuit, and internal voltage references. Conversion is controlled by a single clock input.

MT55L256L18P1T-10A

Abstract: MS-026 MT55L128L32P1 MT55L128L36P1 MT55L128V32P1 MT55L128V36P1 MT55L256L18P1 MT55L256L18P1T-10 MT55L256V18P1 84 FBGA thermal
Contextual Info: PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 4Mb ZBT SRAM MT55L256L18P1, MT55L256V18P1, MT55L128L32P1, MT55L128V32P1, MT55L128L36P1, MT55L128V36P1 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • •

A67L7332

Abstract: A67L7336 A67L8316 A67L8318
Contextual Info: A67L8316/A67L8318/ A67L7332/A67L7336 Series 256K X 16/18, 128K X 32/36 Preliminary LVTTL, Pipelined DBA SRAM Document Title 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue

MT58L64L36P

Abstract: MS-026 MT58L128L18P MT58L128V18P MT58L64L32P MT58L64V32P MT58L64V36P
Contextual Info: NOT RECOMENDED FOR NEW DESIGNS 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM 2Mb SYNCBURST SRAM MT58L128L18P, MT58L64L32P, MT58L64L36P; MT58L128V18P, MT58L64V32P, MT58L64V36P 3.3V VDD, 3.3V or 2.5V I/O, Pipelined, SingleCycle Deselect FEATURES

IS61DDB21M36

Abstract: 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI
Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . I May 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

D0-35

Abstract: IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3
Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 4) Synchronous SRAMs 7 Q . May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.

IS61QDB41M36

Abstract: 61QDB41M36 IS61QDB41M36-250M3L D0-35 IS61QDB41M36-250M3 IS61QDB42M18
Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . I April 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.

K7A401800B-QC

Abstract: K7A401809B K7A401809B-QC K7A403200B-QC K7A403209B K7A403209B-QC K7A403609B K7B401825B-QC K7B403225B-QC
Contextual Info: K7A403609B K7A403209B K7A401809B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters

CY7C1339

Contextual Info: fax id: 1109 PRELIMINARY CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

MoSys

Abstract: CL018G tsmc 0.18um MoSys sram embedded BWEB M1T1HT18PZ32E C-l018 32K32 MoSys 1T sram
Contextual Info: High Speed Pipelined 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PZ32E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late-late write mode timing • 32-Bit wide data buses

GS8161Z18AT-300

Abstract: gs816
Contextual Info: Preliminary GS8161Z18/36AT-300/275/250/225/200 18Mb Pipelined and Flow Through Synchronous NBT SRAM Flow Through 2-1-1-1 1.8 V 2.5 V 300 345 300 340 275 320 275 315 250 295 250 285 230 265 225 260 mA mA mA mA tKQ tCycle 5.0 5.0 5.25 5.25 5.5 5.5 6.0 6.0 6.5