PHASE LOGIC LOOP Search Results
PHASE LOGIC LOOP Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| 54F181LM/B | Rochester Electronics LLC | 54F181 - 4-Bit Arithmetic Logic Unit |
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| 100324/VYA | Rochester Electronics LLC | 100324 - TTL to ECL Translator, 6 Func, Complementary Output, ECL - Dual marked (5962-9153001VYA) |
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| EP1800ILC-70 | Rochester Electronics LLC | EP1800 - Classic Family EPLD |
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| EP600DM-30/B | Rochester Electronics LLC | EP600 - Rochester Manufactured EP600, LOGIC (EPLD) |
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| EP600DM-25/B | Rochester Electronics LLC | EP600 - Rochester Manufactured EP600, LOGIC (EPLD) |
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PHASE LOGIC LOOP Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
AND8040
Abstract: AND8040/D MC100EP40 MC100LVEL40 PRAD-2
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Original |
and8040/dand8040mc100ep40mc100lvel40+1 | |
AND8040
Abstract: ko 247 MC100LVEL40
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Original |
and8040/dr14525and8040ko 247+1 | |
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Contextual Info: Figure 1. Block Diagram F l F l F I F I F ] □ _ Clock Doubler/ Ttoo-Phase Generator PHASE-LOCKED CONTROL LOGIC LOOP P IL \ MUX DIVIDE "0 OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER LlJ Li] /— Oata Sheets F l GA1210E LOGIC OUTPUT BUFFER lD OUTPUT BUFFER |
OCR Scan |
ga1210e500ps16-pin28-pin | |
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Contextual Info: T R I Q U I N T S E M I C O N D U C T O R, I N C . GA1110E Figure 1. Block Diagram VDD T1 CLKIN FBIN S1 S0 T0 GND 8 7 6 5 4 3 2 1 PHASE-LOCKED LOOP PLL PHASE CONTROL LOGIC Multi-Phase Clock Buffer MUX CONFIGURATION LOGIC Features GND OUTPUT BUFFER OUTPUT |
Original |
ga1110e | |
diode BY 399 itt
Abstract: Q20P010 M/Q20P025
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OCR Scan |
q2000010opstogp010q20p025+6 | |
MC4044
Abstract: mecl mttl MTTL MC12013 648 ANALOG MC4024 MC12000 MC12012 MC12020 phase logic loop
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OCR Scan |
mc12000mc1658mc4024mc4044+9 | |
MOTION DETECTOR opampContextual Info: UC1634 UC2634 UC3634 UNITRODE Phase Locked Frequency Controller DESCRIPTION FEATURES Precision Phase Locked Frequency Control System Communication Logic for 2-Phase Motors Disable Input for Motor Inhibit Crystal Oscillator Programmable Reference Frequency Dividers |
OCR Scan |
uc1634uc2634uc3634uc1633+2 | |
SCHS177B
Abstract: CD74HC297E HC297 CD74HC297
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Original |
cd54hc297cd74hc297cd74hct297schs177b+2 | |
CD54HC297
Abstract: CD74HCT297 CD54HC297F3A CD74HC297 CD74HC297E LH211
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hc297hct29cd54hc297cd74hc297+7 | |
CD74HCT297EContextual Info: [ /Title CD74 HC297 , CD74 HCT29 7 /Subject (HighSpeed CMOS Logic Digital PhaseLocked CD54HC297, CD74HC297, CD74HCT297 Data sheet acquired from Harris Semiconductor SCHS177B High-Speed CMOS Logic Digital Phase-Locked Loop November 1997 - Revised May 2003 |
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cd54hc297cd74hc297cd74hct297schs177b+2 | |
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Contextual Info: [ /Title CD74 HC297 , CD74 HCT29 7 /Subject (HighSpeed CMOS Logic Digital PhaseLocked CD54HC297, CD74HC297, CD74HCT297 Data sheet acquired from Harris Semiconductor SCHS177B High-Speed CMOS Logic Digital Phase-Locked Loop November 1997 - Revised May 2003 |
Original |
hc297hct29cd54hc297cd74hc297+4 | |
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Contextual Info: [ /Title CD74 HC297 , CD74 HCT29 7 /Subject (HighSpeed CMOS Logic Digital PhaseLocked CD54HC297, CD74HC297, CD74HCT297 Data sheet acquired from Harris Semiconductor SCHS177B High-Speed CMOS Logic Digital Phase-Locked Loop November 1997 - Revised May 2003 |
Original |
cd54hc297cd74hc297cd74hct297schs177b+1 | |
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Contextual Info: [ /Title CD74 HC297 , CD74 HCT29 7 /Subject (HighSpeed CMOS Logic Digital PhaseLocked CD54HC297, CD74HC297, CD74HCT297 Data sheet acquired from Harris Semiconductor SCHS177B High-Speed CMOS Logic Digital Phase-Locked Loop November 1997 - Revised May 2003 |
Original |
cd54hc297cd74hc297cd74hct297schs177b+1 | |
HC297
Abstract: CD54HC297 CD54HC297F3A CD74HC297 CD74HC297E CD74HCT297
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hc297hct29cd54hc297cd74hc297+6 | |
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CD54HC297
Abstract: CD54HC297F3A CD74HC297 CD74HC297E CD74HCT297
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hc297hct29cd54hc297cd74hc297+6 | |
CD54HC297
Abstract: CD54HC297F3A CD74HC297 CD74HC297E CD74HCT297 square D KCP
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hc297hct29cd54hc297cd74hc297+7 | |
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Contextual Info: [ /Title CD74 HC297 , CD74 HCT29 7 /Subject (HighSpeed CMOS Logic Digital PhaseLocked CD54HC297, CD74HC297, CD74HCT297 Data sheet acquired from Harris Semiconductor SCHS177B High-Speed CMOS Logic Digital Phase-Locked Loop November 1997 - Revised May 2003 |
Original |
cd54hc297cd74hc297cd74hct297schs177b+1 | |
74hc297 application notes
Abstract: SCHA002 HC297 74ls297 SCHA003 74HC297
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Original |
cd54/74hc297cd74hct297schs177ahc297+10 | |
74hc297
Abstract: SCHS177A 74hc297 application notes CD54HC297 CD54HC297F3A CD74HC297 CD74HC297E CD74HCT297
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Original |
hc297hct29cd54/74hc297cd74hct297+9 | |
diagram of light sensitive alarm
Abstract: Digital Alarm Clock 40 pin BLOCK diagram of light sensitive alarm light sensitive alarm PHOTODIODE ALARM CIRCUIT RGR2622 light sensitive alarm circuit digital clock with alarm
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rgr262220-pindiagram of light sensitive alarmdigital alarm clock 40 pin+5 | |
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Contextual Info: Fiber Optic “Light to Logic” Receiver with Clock Recovery Technical Data RGR1551 Features Applications • Light to Logic 20-pin DIP Receiver offers ECL Compatibility • Long Reach, High Performance • Sensitivity -36 dBm • Phase-locked Loop PLL |
Original |
rgr155120-pinop400rgr1551-xx+4 | |
HEF4046BP
Abstract: HEF4046BT HE4000B HEF4046B HEF4046BD
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Original |
he4000bhef4046bhef4046bphef4046bt+1 | |
application of light sensitive alarm
Abstract: RGR1551 light sensitive alarm diagram of light sensitive alarm
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Original |
rgr155120-pinapplication of light sensitive alarmlight sensitive alarm+1 | |
HEF4046B
Abstract: Family Specifications HEF, HEC HE4000B HEF4046BD HEF4046BP HEF4046BT MS-012AC
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Original |
he4000bhef4046bot38-1050g09+6 | |