PECL LOGIC VOLTAGE LEVELS Search Results

60-0005

Contextual Info: VCXO Page 1 of 3 VS9 SERIES: VCXO OSCILLATOR, PECL, +3.3 VDC DESCRIPTION: A crystal controlled, high frequency, highly stable, voltage controlled oscillator, adhering to Positive Emitter Coupled Logic PECL Standards. The output can be Tri-stated to facilitate testing or combined

Contextual Info: CLOCK Page 1 of 2 VS9 SERIES: VCXO OSCILLATOR, PECL, +3.3 VDC DESCRIPTION: A crystal controlled, high frequency, highly stable, voltage controlled oscillator, adhering to Positive Emitter Coupled Logic PECL Standards. The output can be Tri-stated to facilitate testing or combined multiple clocks.

ecl 806

Abstract: CML ECL termination PLE 2 - 25va Vterm pecl logic voltage levels
Contextual Info: Application Note 806 LVPECL, PECL, ECL Logic and Termination March 2009 by: Ken Johnson and Bob Gubser ABSTRACT This application note will highlight characteristics of Pletronics Low Voltage Positive Emitter Coupled Logic LVPECL frequency control products and provide guidance for

m2071

Abstract: M2054 M2057 m2061 M2063 "Voltage Controlled Oscillators" M2051
Contextual Info: FULL SIZE D.I.L. M2051 thru M2057 L2051 thru L2057 M2061 thru M2063 L2061 thru L2063 M2071 thru M2073 L2071 thru L2073 VOLTAGE CONTROLLED OSCILLATORS 10KH PECL Logic, 0° to 70°C Thru-Hole, 5V 1 MHz to 175 MHz PECL 10KH – Thru-Hole VCXOs, 5V These thru-hole VCXOs are designed for

Contextual Info: MAX3822 I/O Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low Voltage Differential Signal (LVDS)

MCH12140

Abstract: MCK12140 application note MAX9382 MAX9382ESA MAX9382EUA MAX9383 MAX9383ESA MAX9383EUA MCK12140
Contextual Info: 19-2234; Rev 1; 11/02 ECL/PECL Phase-Frequency Detectors The MAX9382/MAX9383 feature low propagation and reset delay, making them ideal for high-frequency clock synchronization use. The MAX9382 uses 100K logic levels, has a supply voltage range of VCC - VEE = 4.2V

2FV transistor

Abstract: MCH12140 MCK12140 application note
Contextual Info: 19-2234; Rev 0; 10/01 ECL/PECL Phase-Frequency Detectors The MAX9382/MAX9383 feature low propagation and reset delay, making them ideal for high-frequency clock synchronization use. The MAX9382 uses 100K logic levels, has a supply voltage range of VCC - VEE = 4.2V

Contextual Info: 19-2234; Rev 1; 11/02 ECL/PECL Phase-Frequency Detectors The MAX9382/MAX9383 feature low propagation and reset delay, making them ideal for high-frequency clock synchronization use. The MAX9382 uses 100K logic levels, has a supply voltage range of VCC - VEE = 4.2V

Datasheet MCH12140

Abstract: MAX9383 MAX9382 MAX9382ESA MAX9382EUA MAX9383ESA MAX9383EUA MCH12140 MCK12140 F3070
Contextual Info: 19-2234; Rev 0; 10/01 ECL/PECL Phase-Frequency Detectors The MAX9382/MAX9383 feature low propagation and reset delay, making them ideal for high-frequency clock synchronization use. The MAX9382 uses 100K logic levels, has a supply voltage range of VCC - VEE = 4.2V

VCO-600A

Abstract: L1005 vectron ECL
Contextual Info: Product Data Sheet VCO-600A Voltage Controlled Saw Oscillator Features • Output Frequency @ 155 MHz to 1 GHz • Low jitter, 3pS for 622, 6pS for 155 typical • Ideal for clock smoothing, frequency translation, clock and data retiming applications • 10K ECL, PECL logic levels with fast

VS700LG

Abstract: GR-253-CORE VS-700 VS700
Contextual Info: VS-700 Voltage Controlled SAW Oscillator Features • Industry Standard Package, 5.0 x 7.5 x 2.5 mm • Output Frequencies from 500 MHz to 850 MHz • 3.3 V Operation • Low Jitter < 0.30 ps-rms across 50 kHz to 80 MHz • LV-PECL Logic Levels with Fast Transition Times

VS700LG

Abstract: 70 MHz SAW FILTER
Contextual Info: VS-700 Voltage Controlled SAW Oscillator Features • Industry Standard Package, 5.0 x 7.5 x 2.5 mm • Output Frequencies from 500 MHz to 850 MHz • 3.3 V Operation • Low Jitter < 0.5 ps-rms across 50 kHz to 80 MHz • LV-PECL Logic Levels with Fast Transition Times

311040M

Abstract: VCO-600A od3 tube
Contextual Info: Product Data Sheet VCO-600A Voltage Controlled Saw Oscillator Features • Output Frequency @ 155 MHz to 1 GHz • Low jitter, 1.5pS for 622, 3pS for 155 typical • Ideal for clock smoothing, frequency translation, clock and data retiming applications • 10K ECL, PECL logic levels with fast transition times

Contextual Info: FS6058-01 LVPECL to HCSL/LVTTL Motherboard Clock Driver IC 1.0 • Figure 2: Pin Configuration Features Distributes one differential LVPECL reference clock to six differential HCSL clock pairs and two singleended LVTTL MREF clocks HCSL current levels controlled by IREF current

F100K

Abstract: SY100S391 SY100S391FC SY100S391JC SY100S391JCTR
Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow

Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to D ifferential PECL Translator M C10ELT22 M C100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA TTL to Differential PECL Translator MC10ELT20 MC100ELT20 The MC1OELT/100ELT20 is a TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

AZ100ELT23

Contextual Info: AZ100ELT23 Dual Differential PECL to CMOS/TTL Translator www.azmicrotek.com DESCRIPTION The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL Positive ECL levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator MC10ELT22 MC100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator MC10ELT22 MC100ELT22 The M C 10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The sm all outline 8-lead SOIC package and the low skew, dual

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to D ifferential PECL Translator M C10ELT22 M C100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual Differential PECL to TTL Translator MC100ELT23 The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the dual gate

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual Differential PECL to TTL Translator MC100ELT23 The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the