PECL LOGIC VOLTAGE LEVELS Search Results

m2071

Abstract: M2054 M2057 m2061 M2063 "Voltage Controlled Oscillators" M2051
Contextual Info: FULL SIZE D.I.L. M2051 thru M2057 L2051 thru L2057 M2061 thru M2063 L2061 thru L2063 M2071 thru M2073 L2071 thru L2073 VOLTAGE CONTROLLED OSCILLATORS 10KH PECL Logic, 0° to 70°C Thru-Hole, 5V 1 MHz to 175 MHz PECL 10KH – Thru-Hole VCXOs, 5V These thru-hole VCXOs are designed for

Contextual Info: MAX3822 I/O Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low Voltage Differential Signal (LVDS)

Contextual Info: « 01/Iie n /« V LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FEATURES PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one

F100K

Abstract: SY100S391 SY100S391FC SY100S391JC SY100S391JCTR
Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA TTL to Differential PECL Translator MC10ELT20 MC100ELT20 The MC1OELT/100ELT20 is a TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator MC10ELT22 MC100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual Differential PECL to TTL Translator MC100ELT23 The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the dual gate

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Differential PECL to TTL Translator MC10ELT21 MC100ELT21 The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual D ifferential PECL to TTL Translator M C100ELT23 The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the dual gate

Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR Micrel, Inc. FEATURES • ■ ■ ■ SY100S391 SY100S391 DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation

Contextual Info: M OTOROLA SEMICONDUCTOR TECHNICAL DATA Differential PECL to TTL Translator MC10ELT21 MC100ELT21 The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

7252 motorola

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Differential PECL to TTL Translator MC10ELT21 MC100ELT21 The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of the

Contextual Info: M OTOROLA SEMICONDUCTOR TECHNICAL DATA TTL to Differential PECL Translator MC10ELT20 MC100ELT20 The MC10ELT/100ELT20 is a TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

1562500mhz

Abstract: SEL382
Contextual Info: SEL382 Series 2.5V PECL Low Jitter Crystal Clock Oscillator XO Actual Size = 5 x 7mm Product Features • Less than 1 ps RMS jitter with advanced non-PLL, patent-pending design 2.00 max .079 • 2.5V PECL (LVPECL) compatible logic levels • Pin-compatible with standard 5x7mm packages

Contextual Info: V PRELIMINARY SY10ELT22L SY100ELT22L d u a l t t l -t o - d if f e r e n t ia l SYNERGY p e c l tr a n s la to r SEMICONDUCTOR DESCRIPTION FEATURES The SY10ELT/100ELT22L are dual TTL-to-differential PECL translators. Because PECL Positive ECL levels are used, only +3.3V and ground are required. The small

KLT20

Abstract: HLT20 SO-8 HLT20 TSSOP-8 socket ic so8 socket
Contextual Info: MC10ELT20, MC100ELT20 5V TTL to Differential PECL Translator The MC10ELT/100ELT20 is a TTL to differential PECL translator. Because PECL Positive ECL levels are used, only +5 V and ground are required. The small outline 8-lead package and the single gate of

Contextual Info: ClockWorks SY10ELT21 ClockWorks™ SY100ELT21 DIFFERENTIAL PECL-to-TTL TRANSLATOR SYNERGY SY10ELT21 SY100ELT21 SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ ■ DESCRIPTION The SY10/100ELT21 are single differential PECL-toTTL translators. Because PECL Positive ECL levels are

ELT21

Abstract: SY100ELT21 SY100ELT21ZC SY10ELT21 SY10ELT21ZC SY10ELT21ZCTR
Contextual Info: DIFFERENTIAL PECL-to-TTL TRANSLATOR FEATURES • ■ ■ ■ ■ ■ ClockWorks SY10ELT21 SY100ELT21 DESCRIPTION The SY10/100ELT21 are single differential PECL-toTTL translators. Because PECL Positive ECL levels are used, only +5V and ground are required. The small outline

DL140

Abstract: ELT22 MC100ELT22 MC10ELT22
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator MC10ELT22 MC100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual

Contextual Info: « LOW-P'OWERHEX TTL-TO-PECL TRANSLATOR SYNERGY PRELIMINARY SY100S391 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logiclevels. Theunique feature of this translator is the ability to do this translation

DL140

Abstract: ELT20 MC100ELT20 MC10ELT20
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA TTL to Differential PECL Translator MC10ELT20 MC100ELT20 The MC10ELT/100ELT20 is a TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

Contextual Info: V SYNERGY DUA LTTL-tO -DIFFERENTIAL PECL TRANSLATOR SY10ELT22 SY100ELT22 S E M IC O N D U C T O R DESCRIPTION FEATURES 300ps typical propagation delay The S Y 10/100ELT22 are dual T TL-to-differential PECL translators. Because PECL P ositive ECL levels are

8-pin 3773

Abstract: 100ELT21 3773
Contextual Info: SK10/100ELT21W Differential PECL to CMOS/TTL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100ELT21W is a single differential PECL to CMOS/TTL Translator. Since PECL Positive ECL levels are used, only +VCC and ground are required.

100391PC

Abstract: 100391QC 100391QI 100391SC F100K M24B MO-047 MS-011 MS-013 N24E
Contextual Info: Revised November 1999 100391 Low Power Single Supply Hex TTL-to-PECL Translator General Description Features The 100391 is a hex translator for converting TTL logic levels to F100K PECL logic levels. The unique feature of this translator, is the ability to do this translation using only one