PD02S Search Results

Contextual Info: >4MCC Q20000 "T U R B O ECL/TTL TIMING VERNIERS TIMING VERNIER PD01S Figure 16. Functional Block Diagram The PD01S is a programmable delay macro in the Q20000 TU R B O ” family that provides a timing genera­ tion or deskew function for precision timing applications

Q20P010

Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Contextual Info: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability

Contextual Info: - H Y U N D A I ♦ HYM7V75AR400C N-SERIES > Registered 4Mx72 bit SDRAM MODULE based on 4Mx4 SDRAM, LVTTL, 4K-Refresh DESCRIPTION The HYM7V75AR400C is a high speed 3.3Volt Synchronous Dynamic RAM module consisting of eighteen 4Mx4 bit Synchronous DRAMs in TSO PII and one 8-pin T S S O P 2K bit EEPRO M on a 168-pin glass-epoxy