PCI CORE Search Results

PCI CORE Result Highlights (5)

Part	Manufacturer	Description	Download
AM79C961AVI	Rochester Electronics LLC	Full Duplex 10/100 MBPS ETHERNET Controller for PCI Local Bus, PCNET- ISA II jumperless	PDF
AM79C961AVC\\W	Rochester Electronics LLC	Full Duplex 10/100 MBPS ETHERNET Controller for PCI Local Bus, PCNET- ISA II jumperless	PDF
TDS4B212MX	Toshiba Electronic Devices & Storage Corporation	PCI Express switch, 2 Differential Channel, 2:1 multiplexer/1:2 demultiplexer, SPDT, XQFN16	Datasheet
TDS4A212MX	Toshiba Electronic Devices & Storage Corporation	PCI Express switch, 2 Differential Channel, 2:1 multiplexer/1:2 demultiplexer, SPDT, XQFN16	Datasheet
TMPM330FWFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/LQFP100-P-1414-0.50H	Datasheet

PCI CORE Datasheets (1)

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Lattice Semiconductor

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
PCI Core		Lattice Semiconductor	PCI Core Data Sheet	Original	PDF	536.73KB	12

PCI CORE Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
PCI AHB DMA Abstract: ahb slave RTL AMBA AHB bus AMBA AHB DMA DMA with AHB PCI AHB bridge Contextual Info:  PCI specification 2.3 compliant  66MHz PCI performance  64-bit PCI data path PCI-M64AHB  Zero wait states burst mode  Full PCI bus master/target func- 64-bit/66MHz PCI PCI to AMBA AHB Interface Core tionality  Single PCI interrupt support	Original	66mhz 64-bit pci-m64ahb 64-bit/66mhz +6pci ahb dma ahb slave rtl amba ahb bus amba ahb dma dma with ahb pci ahb bridge	PDF
ACP11 Contextual Info: PCI2031 PCI-TO-PCI BRIDGE SCPSQ17A - DECEMBER 1997 - REVISED JANUARY 1998 PCI Power Management Compliant ACP11.0 Compliant Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V	OCR Scan	pci2031 scpsq17a acp11 32-bit +133-mhz	PDF
Spartan-3E XC3S1600E-4 Abstract: vhdl code for 32bit data memory XC2V1000-4 Contextual Info: PCI specification 2.3 compliant 33/66 MHz performance 32-bit datapath PCI-HB 32-bit/33, 66MHz PCI Host Bridge Core The PCI Host Bridge core enables data transfers between a host processor system and PCI bus based devices. The bridge is in charge of PCI bus arbitration, generating PCI	Original	32-bit 32-bit/33 66mhz spartan-3e xc3s1600e-4 +2vhdl code for 32bit data memory xc2v1000-4	PDF
PCI2030 Abstract: AD27 AD29 AD30 XCPS012 S-PQFP-G176 Contextual Info: PCI2030 PCI-TO-PCI BRIDGE XCPS012 – DECEMBER 1997 D D D D D D D D D D D D Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments	Original	pci2030 xcps012 32-bit 33-mhz +4ad27 ad29 ad30 s-pqfp-g176	PDF
AD27 Abstract: AD29 AD30 PCI2030 XCPS012 Contextual Info: PCI2030 PCI-TO-PCI BRIDGE XCPS012 – DECEMBER 1997 D D D D D D D D D D D D Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments	Original	pci2030 xcps012 32-bit 33-mhz +3ad27 ad29 ad30	PDF
AD27 Abstract: AD29 AD30 PCI2031 Contextual Info: PCI2031 PCI-TO-PCI BRIDGE SCPS017A – DECEMBER 1997 – REVISED JANUARY 1998 D D D D D D D D D D D D D PCI Power Management Compliant ACPI 1.0 Compliant Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI	Original	pci2031 scps017a 32-bit 33-mhz +3ad27 ad29 ad30	PDF
south bridge Abstract: AD27 AD29 AD30 PCI2031 678h-67Bh S-PQFP-G176 Contextual Info: PCI2031 PCI-TO-PCI BRIDGE SCPS017A – DECEMBER 1997 – REVISED JANUARY 1998 D D D D D D D D D D D D D PCI Power Management Compliant ACPI 1.0 Compliant Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI	Original	pci2031 scps017a 32-bit 33-mhz +6south bridge ad27 ad29 ad30 678h-67bh s-pqfp-g176	PDF
AD27 Abstract: AD29 AD30 PCI2031 XCPS017 Contextual Info: PCI2031 PCI-TO-PCI BRIDGE XCPS017 – DECEMBER 1997 D D D D D D D D D D PCI Power Management Compliant ACPI 1.0 Compliant Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V	Original	pci2031 xcps017 32-bit 33-mhz +3ad27 ad29 ad30	PDF
PCI Express Abstract: northwest logic pci express verification for pci express PCI express design pci root complex DMA engine PCI express x1 specification Contextual Info: PCI Express Complete Core Block Diagram • Combines Northwest Logic’s PCI Express Core and PCI Express Back-End for a complete, easy-to-use PCI Express Solution PCI Express Back-End • x1, x4, x8 lane versions available • Comprehensive PCI Express PHY support	Original	pci express northwest logic pci express verification for pci express pci express design +3pci root complex dma engine pci express x1 specification	PDF
XC6SLX9 Abstract: Spartan6 XC6SLX9 XC6SL* MEMORY spartan 3e xc3s500e XC3S500E Contextual Info: Fully compliant with the PCI Local Bus Specification, Revision 2.3. PCI-M32MF Multi-Function PCI Master/Target Interface Core The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz 66 MHz	Original	pci-m32mf 32-bit xc6slx9 spartan6 xc6slx9 +3xc6sl* memory spartan 3e xc3s500e xc3s500e	PDF
be3sc Contextual Info: PCI2030 PCI-TO-PCI BRIDGE XCPS012 -D E C E M B E R 1997 • Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 • • • • • • • • • 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V	OCR Scan	pci2030 xcps012 32-bit 33-mhz +1be3sc	PDF
CAN protocol basics Abstract: design desktop motherboard tutorial XC2S50 driver pci card schematic diodes PCI I/O interface PAR64 PCI64 64-BIT SOUND CARD REQ64 Contextual Info: PCI Tutorial PCI Basics - Slide 1 2000 Xilinx, Inc. All Rights Reserved Agenda PCI Fundamentals PCI Local Bus Architecture PCI Configuration PCI Signals Electrical and Timing Specifications Basic Bus Operations 64-bit Extension PCI Addressing and Bus Commands	Original	64-bit 66-mhz differen2000 can protocol basics +9design desktop motherboard tutorial xc2s50 driver pci card schematic diodes pci i/o interface par64 pci64 64-bit sound card req64	PDF
pci core Abstract: Soft Core RTL FIFO synchronous fifo design in verilog Contextual Info: PCI Peripheral Core PCI ADOUT Register Core Block Diagram PCI Parity Multiplexer Register Master Write FIFO PCI Bus Register Master Read FIFO Master State Machine/ DMA Register Master Request FIFO Output Mux Application Interface PCI I/O Cells ▼ Configuration	Original	32-bit 64-bit asic-fs-20827-10/99 pci core +2soft core rtl fifo synchronous fifo design in verilog	PDF
AMBA BUS vhdl code Abstract: amba ahb bus arbitration AMBA AHB memory controller AMBA AHB bus arbiter PCI AHB bridge ahb slave RTL vhdl code AMBA AHB interrupt controller in vhdl code AMBA AHB bus bus arbiter Contextual Info: PCI specification 2.3 compliant 33/66 MHz performance 32-bit datapath PCI-HB-AHB PCI reset generator PCI bus arbiter up to 7 external bus agents 32-bit, 33/66MHz PCI AMBA AHB Host Bridge Core Interrupt controller Parity generation and parity error detection.	Original	32-bit 33/66mhz amba bus vhdl code amba ahb bus arbitration +8amba ahb memory controller amba ahb bus arbiter pci ahb bridge ahb slave rtl vhdl code amba ahb interrupt controller in vhdl code amba ahb bus bus arbiter	PDF

nvidia G86 Abstract: DMS59 DMS-59 1920x1200 nvidia g86-730 DMS59 to vga 2048X1536 P383 NV44NVS VCQ440NVS-PCX16BLK-1 Contextual Info: NVIDIA QUADRO NVS by PNY TECHNOLOGIES Dual - Monitor www.pny.eu Bus Connector NVS 280 PCI P169 NVS 285 PCI-E x1 (P583) Quad - Monitor NVS 285 PCI-E x16 (P383) NVS 290 PCI-E x1 (P558) NVS 290 PCI-E x16 (P538) NVS 440 PCI-E (P498) NVS 440 PCI-E (P307) PCI	Original	g86-825 dms59 2048x1536 1920x1200 +9vcq290nvs-pcx1-pb vcq290nvs-pcx1blk-1 nvidia g86 dms-59 nvidia g86-730 dms59 to vga p383 nv44nvs vcq440nvs-pcx16blk-1	PDF
Ac bridge specifications Abstract: bus arbiter LCMXO280C-4 Contextual Info:  PCI specification 2.3 compliant  33/66 MHz performance  32-bit datapath PCI-HB 32-bit/33, 66MHz PCI Host Bridge Core  PCI reset generator  PCI bus arbiter up to 7 external bus agents  Interrupt controller  Parity generation and parity	Original	32-bit 32-bit/33 66mhz ac bridge specifications +2bus arbiter lcmxo280c-4	PDF
SPARTAN-3 XC3S400 Abstract: vhdl code dma controller XC3S400 vhdl code for parity checker PCI-M32 Spartan 3E VHDL code VIRTEX-5 xc5vlx50 vhdl code for 6 bit parity generator vhdl code for bram XC3S250E Contextual Info: Flexible synthesizable VHDL PCI specification 2.3 compliant PCI-M32 32-bit/33MHz PCI Master/Target Interface Core The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on	Original	pci-m32 32-bit/33mhz 32-bit spartan-3 xc3s400 +8vhdl code dma controller xc3s400 vhdl code for parity checker spartan 3e vhdl code virtex-5 xc5vlx50 vhdl code for 6 bit parity generator vhdl code for bram xc3s250e	PDF
vhdl code dma controller Abstract: VHDL code for pci vhdl code for DMA application of parity checker design of dma controller using vhdl PCI-M32 Contextual Info: Flexible synthesizable VHDL PCI specification 2.3 compliant PCI-M32 32-bit/33MHz PCI Master/Target Interface Core The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on	Original	pci-m32 32-bit/33mhz 32-bit vhdl code dma controller +4vhdl code for pci vhdl code for dma application of parity checker design of dma controller using vhdl	PDF
slot machine block diagram vhdl Abstract: MPCI32 vhdl code dma controller ,vhdl code for implementation of eeprom 32Bit verilog code for pci to pci bridge pci verilog code verilog code for EEPROM Controller Contextual Info: Inventra MPCI32 Soft Core RTL IP 32bit 33/66MHz PCI Core w/Cardbus support PCI Bus / Cardbus D A T A S H E E T Major Product Features: • Fully compliant with PCI v2.2 specification PCI Core for Peripheral Apps. PCI Bus Interface Target Register Interface	Original	mpci32 32bit 33/66mhz pd-40100 +7003-fo slot machine block diagram vhdl vhdl code dma controller vhdl code for implementation of eeprom verilog code for pci to pci bridge pci verilog code verilog code for eeprom controller	PDF
SLC88B17 Contextual Info: SLC88B17 ADVANCE INFORMATION PCI-ISA Bridge Chip FEATURES 5 Volt Operation PCI 2.1 Compliant PCI to ISA bridge - Supports 33MHz PCI bus Supports Full ISA at ¼ of PCI Frequency Supports Full Subtractive Decode of PCI Supports up to 5 ISA Slots Supports PC/PCI DMA Protocol	Original	slc88b17 33mhz slc88b17qfp	PDF
LAB2 Contextual Info: PCI Core Basics pci18000-4-ILT v1.0 September 08, 2003 Course Specification Course Description This PCI training course gives you an introduction to basic PCI concepts and architecture. This course emphasizes and illustrates how PCI transactions take place. It also gives you an overview of Xilinx PCI	Original	pci18000-4-ilt 64-bit 66-mhz lab2	PDF
Contextual Info:  PCI specification 2.3 compliant  33/66 MHz performance  32-bit datapath PCI-HB 32-bit/33, 66Mhz PCI Host Bridge Core  PCI reset generator  PCI bus arbiter up to 7 external bus agents  Interrupt controller  Parity generation and parity	Original	32-bit 32-bit/33 66mhz	PDF
application of parity checker Abstract: design of dma controller using vhdl PCI-M32 vhdl code it parity generator sample vhdl code for memory write VHDL code for pci RTAX250S Contextual Info: Flexible synthesizable VHDL PCI specification 2.3 compliant PCI-M32 32-bit/33MHz PCI Master/Target Interface Core The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on	Original	pci-m32 32-bit/33mhz 32-bit application of parity checker +5design of dma controller using vhdl vhdl code it parity generator sample vhdl code for memory write vhdl code for pci rtax250s	PDF
AD10 Abstract: AD11 AD12 PCI2050 PCI2050A Contextual Info: PCI2050A PCI-to-PCI BRIDGE SCPS067 – MAY 2001 D D D D D D D Two 32-Bit, 66-MHz PCI Buses Configurable for PCI Power Management Interface Specification Provides CompactPCI Hot-Swap Functionality 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V	Original	pci2050a scps067 32-bit 66-mhz +4ad10 ad11 ad12 pci2050	PDF

PCI CORE Search Results

PCI CORE Result Highlights (5)

PCI CORE Datasheets (1)

PCI CORE Datasheets Context Search

PCI AHB DMA

ACP11

Spartan-3E XC3S1600E-4

PCI2030

AD27

AD27

south bridge

AD27

PCI Express

XC6SLX9

be3sc

CAN protocol basics

pci core

AMBA BUS vhdl code

nvidia G86

Ac bridge specifications

SPARTAN-3 XC3S400

vhdl code dma controller

slot machine block diagram vhdl

SLC88B17

LAB2

application of parity checker

AD10