vhdl code fro complex multiplication and addition
Abstract: 64 bit cpci backplane 100K preset horizontal ldr block diagram verilog code for implementation of eeprom vhdl code 16 bit processor 25G01K100 CYS25G01K100 STM-16
Contextual Info: CYS25G01K100V1 2.5-Gbps Programmable Serial Interface Features — Copper cables • High-speed HS Programmable Serial Interface™ (PSI™) • 2.48- to 2.5-Gbps serial signaling rate • Full Bellcore and ITU jitter compliance • Flexible parallel-to-serial conversion in transmit path
|
Original
|
cys25g01k100v1cys25g01k100cyp25g01k100vhdl code fro complex multiplication and addition+764 bit cpci backplane100k preset horizontalldr block diagramverilog code for implementation of eepromvhdl code 16 bit processor25g01k100stm-16
|
PDF
|
vhdl code fro complex multiplication and addition
Abstract: 25G01K100 CYS25G01K100 STM-16
Contextual Info: 2.5-Gbps Programmable Serial Interface Features — Circuit board traces — Backplane links • High-speed HS Programmable Serial Interface™ (PSI™) • 2.48- to 2.5-Gbps serial signaling rate • Full Bellcore and ITU jitter compliance • Flexible parallel-to-serial conversion in transmit path
|
Original
|
cys25g01k100vhdl code fro complex multiplication and addition25g01k100stm-16 |
PDF
|
|
Contextual Info: Programmable Serial Interface Family High Speed PRELIMINARY Programmable Bandwidth Features • • • • • • • • • • • • • • • • 200 Mbps – 1.5 Gbps, 2.5 Gbps serial signaling rate Flexible parallel-to-serial conversion in transmit path
|
Original
|
|
PDF
|
456-BGA
Abstract: 45x45 bga 8kx1 RAM LB 156 15G04K100 15G04K200 25G01K100 25G02K100
Contextual Info: Programmable Serial Interface High Speed Devices PRELIMINARY Programmable Bandwidth Features • • • • • • • • • • • • • • • • 200 Mbps–1.5 Gbps, 2.5 Gbps serial signaling rate Flexible parallel-to-serial conversion in transmit path
|
Original
|
456-bga45x45 bga8kx1 ramlb 156+415g04k10015g04k20025g01k10025g02k100
|
PDF
|
PSI5 transceiver
Contextual Info: Programmable Serial Interface PRELIMINARY Device Family High Speed Programmable Bandwidth Features • • • • • • • • • • • • • • • • 200 Mbps – 1.5 Gbps, 2.5 Gbps serial signaling rate Flexible parallel-to-serial conversion in transmit path
|
Original
|
psi5 transceiver |
PDF
|
45x45 bga
Abstract: 15G04K100 15G04K200 25G01K100 25G02K100
Contextual Info: Programmable Serial Interface PRELIMINARY High Speed Devices Programmable Bandwidth Features • • • • • • • • • • • • • • • • 200 Mbps – 1.5 Gbps, 2.5 Gbps serial signaling rate Flexible parallel-to-serial conversion in transmit path
|
Original
|
384kb45x45 bga15g04k10015g04k200+225g01k10025g02k100
|
PDF
|
intel 8250
Abstract: 8250 uart intel 8250 intel uart intel 8250 UART 8250 intel 8250 uart block diagram 8250 uart EP1K10 EP20K30E EPF10K30E
Contextual Info: H8250 Megafunction Universal Asynchronous Receiver/Transmitter General Description Features The H8250 is a standard UART providing 100% software compatibility with the popular Intel 8250 device. It performs serial-to-parallel conversion on data originating from modems or other serial
|
Original
|
h8250intel 82508250 uart intel8250 intel uart+7intel 8250 uart8250 intel8250 uart block diagram8250 uartep1k10ep20k30eepf10k30e
|
PDF
|
intel 8250
Abstract: intel 8250 UART 8250 intel 8250 uart intel 8250 intel uart vhdl code for 8 bit ODD parity generator 8250 uart datasheet verilog hdl code for parity generator uart 8250 configuration 8250 uart
Contextual Info: H8250 Megafunction Universal Asynchronous Receiver/Transmitter General Description Features The H8250 is a standard UART providing 100% software compatibility with the popular Intel 8250 device. It performs serial-to-parallel conversion on data originating from modems or other serial
|
Original
|
h8250intel 8250intel 8250 uart8250 intel+78250 uart intel8250 intel uartvhdl code for 8 bit odd parity generator8250 uart datasheetverilog hdl code for parity generatoruart 8250configuration 8250 uart
|
PDF
|
FRS transceiver
Abstract: CYP15G04K100V1-MGC verilog code 5 bit LFSR micro sd verilog MODEL
Contextual Info: PRELIMINARY CYP15G04K100V1-MGC CYP15G04K200V2-MGC Programmable Serial Interface Frequency Agile Devices Features • • • • • • • • • • • • • • • • 200 Mbps–1.5 Gbps, 2.5 Gbps serial signaling rate Flexible parallel-to-serial conversion in transmit path
|
Original
|
cyp15g04k100v1-mgccyp15g04k200v2-mgccyp15g04k100v1-mgc/cyp15g04k200v2-mgcfrs transceiver+2verilog code 5 bit lfsrmicro sd verilog model
|
PDF
|
"Single-Port RAM"
Abstract: PSI2G100S
Contextual Info: CYPSI: Revision: March 21, 2001 Programmable Serial Interface Family High Speed PRELIMINARY Programmable Bandwidth Features • • • • • • • • • • • • • • • • 200 Mbps – 1.5 Gbps, 2.5 Gbps serial signaling rate Flexible parallel-to-serial conversion in transmit path
|
Original
|
single-port rampsi2g100s |
PDF
|
verilog code 16 bit processor
Abstract: uart vhdl code fpga verilog hdl code for parity generator verilog code for ring counter D16450 verilog code for 8 bit shift register APEX20K APEX20KE D16550 FLEX10KE
Contextual Info: D16450 Configurable UART ver 2.07 OVERVIEW The D16450 is a soft Core of a Universal Asynchronous Receiver/Transmitter UART functionally identical to the TL16C450. D16450 performs serial-to-parallel conversion on data characters received from a peripheral
|
Original
|
d16450tl16c450verilog code 16 bit processoruart vhdl code fpga+7verilog hdl code for parity generatorverilog code for ring counterverilog code for 8 bit shift registerapex20kapex20ked16550flex10ke
|
PDF
|
verilog code for UART baud rate generator
Abstract: H16450S EP1K10 EP20K30E EPF10K30E R 433 transmitter block diagram baud rate generator vhdl verilog code for baud rate generator
Contextual Info: H16450S Megafunction Universal Asynchronous Receiver/Transmitter General Description Features The H16450S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16450 device. It performs serial-to-parallel conversion on data originating
|
Original
|
h16450sverilog code for uart baud rate generatorep1k10ep20k30e+4epf10k30er 433 transmitter block diagrambaud rate generator vhdlverilog code for baud rate generator
|
PDF
|
verilog code for baud rate generator
Abstract: uart vhdl h16750 verilog code for UART baud rate generator IrDa port synchronous fifo design in verilog baud rate generator vhdl vhdl code 16 bit processor H16750S H16750
Contextual Info: H16750S Universal Asynchronous Receiver/Transmitter with FIFOs Megafunction General Description Features The H16750S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel conversion on data originating
|
Original
|
h16750s16450compatibleverilog code for baud rate generatoruart vhdl h16750+6verilog code for uart baud rate generatorirda portsynchronous fifo design in verilogbaud rate generator vhdlvhdl code 16 bit processorh16750
|
PDF
|
block diagram UART using VHDL
Abstract: wishbone interface for UART LCMXO2-1200HC-4TG144C FSM VHDL interface of rs232 to UART in VHDL LFXP2-5E-5TN144C Lattice LFXP2 NS16450 RD1042 uart verilog testbench
Contextual Info: WISHBONE UART November 2010 Reference Design RD1042 Introduction The Lattice WISHBONE UART provides an interface between the WISHBONE UART system bus and an RS232 serial communication channel. Figure 1 shows the major blocks implemented in the UART in non-FIFO mode. This UART reference design contains a receiver and a transmitter. The receiver performs serial-to-parallel conversion on the asynchronous data
|
Original
|
rd1042rs232latticemico321-800-lattice+9block diagram uart using vhdlwishbone interface for uartlcmxo2-1200hc-4tg144cfsm vhdlinterface of rs232 to uart in vhdllfxp2-5e-5tn144clattice lfxp2ns16450uart verilog testbench
|
PDF
|
|
|
xilinx uart verilog code
Abstract: vhdl code for rs232 receiver vhdl code for uart communication vhdl code for shift register vhdl code for serial transmitter 16 bit register vhdl vhdl code for rs232 interface UART using VHDL uart verilog code vhdl code for 8 bit shift register
Contextual Info: Application Note: CPLD R UARTs in Xilinx CPLDs XAPP341 v1.1 April 17, 2000 Summary This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144 and XCR3128 CPLDs. The functionality of the
|
Original
|
xapp341xc95144xcr3128rs232+10xilinx uart verilog codevhdl code for rs232 receivervhdl code for uart communicationvhdl code for shift registervhdl code for serial transmitter16 bit register vhdlvhdl code for rs232 interfaceuart using vhdluart verilog codevhdl code for 8 bit shift register
|
PDF
|
vhdl code for rs232 receiver
Abstract: xilinx uart verilog code interface of rs232 to UART in VHDL vhdl code for uart communication vhdl code for serial transmitter vhdl code 16 bit microprocessor uart verilog code verilog code for serial transmitter verilog code for 8 bit shift register parallel to serial conversion vhdl
Contextual Info: Application Note: CPLD R UARTs in Xilinx CPLDs XAPP341 v1.3 October 1, 2002 Summary This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144, XCR3128XL, or XC2C128 CPLDs. The
|
Original
|
xapp341xc95144xcr3128xlxc2c128+12rs232xcr3128vhdl code for rs232 receiverxilinx uart verilog codeinterface of rs232 to uart in vhdlvhdl code for uart communicationvhdl code for serial transmittervhdl code 16 bit microprocessoruart verilog codeverilog code for serial transmitterverilog code for 8 bit shift registerparallel to serial conversion vhdl
|
PDF
|
vhdl code manchester encoder
Abstract: vhdl code for manchester decoder vhdl code for clock and data recovery manchester verilog decoder manchester encoder manchester code verilog vhdl code for nrz vhdl manchester vhdl manchester encoder manchester encoder xilinx
Contextual Info: Application Note: CoolRunner CPLDs R XAPP339 v1.2 Jaunary 10, 2001 Manchester Encoder-Decoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are discussed. The code
|
Original
|
xapp339xc9572xcr3064xlvhdl code manchester encoder+9vhdl code for manchester decodervhdl code for clock and data recoverymanchester verilog decodermanchester encodermanchester code verilogvhdl code for nrzvhdl manchestervhdl manchester encodermanchester encoder xilinx
|
PDF
|
vhdl code manchester encoder
Abstract: manchester verilog decoder manchester code verilog line code manchester vhdl manchester vhdl code for nrz Manchester code vhdl code for manchester decoder vhdl code for binary data serial transmitter vhdl code for clock and data recovery
Contextual Info: Application Note: CoolRunner CPLDs R XAPP339 v1.1 April 17, 2000 Manchester Encoder-Decoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are discussed. The code
|
Original
|
xapp339xc9572xcr3064xlvhdl code manchester encoder+9manchester verilog decodermanchester code verilogline code manchestervhdl manchestervhdl code for nrzmanchester codevhdl code for manchester decodervhdl code for binary data serial transmittervhdl code for clock and data recovery
|
PDF
|
cyclic redundancy check verilog source
Abstract: vhdl code manchester encoder vhdl code for manchester decoder vhdl code for clock and data recovery manchester code vhdl manchester verilog code for uart communication manchester manchester verilog decoder vhdl code for uart communication
Contextual Info: Application Note: CoolRunner CPLDs R XAPP339 v1.3 October 1, 2002 Manchester Encoder-Decoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are discussed. The code
|
Original
|
xapp339xc9572xcr3064xlxc2c64+10cyclic redundancy check verilog sourcevhdl code manchester encodervhdl code for manchester decodervhdl code for clock and data recoverymanchester codevhdl manchesterverilog code for uart communicationmanchestermanchester verilog decodervhdl code for uart communication
|
PDF
|
parallel to serial conversion verilog
Abstract: uart verilog testbench H16450 transmitter vhdl UART verification IP XC2V80 XC2S50E-7
Contextual Info: H16450 — Universal Asynchronous Receiver/Transmitter April 5, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Core documentation EDIF Netlist; VHDL & Verilog Design File Formats Source RTL available at extra
|
Original
|
h16450parallel to serial conversion veriloguart verilog testbenchtransmitter vhdl+3uart verification ipxc2v80xc2s50e-7
|
PDF
|
asynchronous fifo vhdl xilinx
Abstract: 16550A UART texas instruments uart verilog testbench fifo vhdl xilinx parallel to serial conversion vhdl H16550S XILINX FIFO UART XC2V80 XC2S50E-7
Contextual Info: H16550S — Universal Asynchronous Receiver/ Transmitter with FIFOs April 5, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Core documentation EDIF Netlist; VHDL Source RTL Design File Formats available at extra cost
|
Original
|
h16550sasynchronous fifo vhdl xilinx16550a uart texas instrumentsuart verilog testbench+5fifo vhdl xilinxparallel to serial conversion vhdlxilinx fifo uartxc2v80xc2s50e-7
|
PDF
|
H16550
Abstract: xilinx asynchronous fifo baud rate generator vhdl XC2V80 XC2S50E-7
Contextual Info: H16550 - Universal Asynchronous Receiver/Transmitter with FIFOs April 5, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Core documentation EDIF Netlist; VHDL Source RTL Design File Formats available at extra cost
|
Original
|
h16550xilinx asynchronous fifobaud rate generator vhdlxc2v80+1xc2s50e-7
|
PDF
|
vhdl code for parallel to serial converter
Abstract: vhdl code for 4-bit counter synchronous dual port ram 16*8 verilog code 16x8 dual ram verilog code for image rotation vhdl code for 8 bit ram parallel to serial conversion verilog serial to parallel converter in vhdl XAPP194 vhdl code for 4 bit ram
Contextual Info: Application Note: Virtex Series R Serial-to-Parallel Converter Author: Paul Gigliotti XAPP194 v.1.0 July 20, 2004 Summary This application note describes the transformation of multiple synchronous serial data streams to parallel data through a multi-channel Serial-to-Parallel Converter. The design, the system
|
Original
|
xapp194vhdl code for parallel to serial convertervhdl code for 4-bit countersynchronous dual port ram 16*8 verilog code+616x8 dual ramverilog code for image rotationvhdl code for 8 bit ramparallel to serial conversion verilogserial to parallel converter in vhdlvhdl code for 4 bit ram
|
PDF
|
LATTICE plsi 3000 SERIES cpld
Abstract: EPM9000 TEMIC PLD EPF8000 actel a1240 actel act1 family pLSI2000 A1415-A14100 EPM5000 Actel a1280 pinout
Contextual Info: Device Specific Device Specific Conversion Information Actel FPGA Conversion FPGA Description RAM Actel devices come in seven families for which ULC conversions are supported: ACT1 A1010, A1020 , ACT2 (A1225, A1240 and A1280), ACT3 (A1415-A14100), ACTEL 40MX and 42MX, the
|
Original
|
a1010a1020a1225a1240+14a1280a1415-a141001200xl3200xepf10k20tc144lattice plsi 3000 series cpldepm9000temic pldepf8000actel a1240actel act1 familyplsi2000epm5000actel a1280 pinout
|
PDF
|
