P368 Search Results

transistor mosfet irf9530

Abstract: IRF9530 transistor irf9530
Contextual Info: Tem ic IRF9530 Siliconix P-Channel Enhancement-Mode Transistor Product Summary V BR DSS (V) r DS(on) ( ß ) I d (A) -1 0 0 0.30 -1 2 TO-220AB “ Ö " Top View P-Channel MOSFET Absolute Maximum Ratings (Tc = 25 °C Unless Otherwise Noted) Parameter Symbol

SMU30N03-30L

Abstract: q3020 smu30n03 SMD30N03-30L
Contextual Info: Tem ic SMD/SMU30N03-30L S em i co n d u c t or s N-Channel Enhancement-Mode Transistors, Logic Level Product Summary VDS V IDa (A) r DS(on) ( ^ ) 0.030 30 30 TO-251 TO-252 D P o o H r Drain Connected to Tab G D S Top View Ô G D S Top View Order Number:

SMP25N05-45L

Contextual Info: Tem ic SMP25N05-45L Siliconix N-Chaniiel Enhancement-Mode Transistor, Logic Level 175 °C Maximum Junction Temperature Product Summary Jd IA 0.045 @ V qs = 10 V 25 0.060 @ VGS = 4.25 V 25 50 D O TO-220AB o .►JE D rain C o n n e c ted to Tab G D S Top View

SMW60N06-18

Abstract: smw60n06
Contextual Info: Tem ic SMW60N06-18 Siliconix N-Channel Enhancement-Mode Transistor, 18-mQ rDS on Product Summary V(BR)DSS (V ) r DS(on) ( Q ) ID (A) 60 0.018 60 TO-247AD Ô s N-Channel M OSFET Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted) Symbol Limit Drain-Source Voltage

SMP30N10

Abstract: P N-Channel D-S MOSFET
Contextual Info: ^ EMIC SMP30N10 Sem i co n d u c t or s N-Channel Enhancement-Mode Transistor Product Summary V BR DSS (V) I d (A) r DS(on) ( ^ ) 0.060 100 30 D O TO-220AB o .J l DRAIN connected to TAB o GD S s Top View N-Channel MOSFET Absolute Maximum Ratings (Tc = 25 °C Unless Otherwise Noted)

irfd9120

Abstract: IRFD9123 IRFD9123 Siliconix
Contextual Info: Tem ic IRFD9120/9123 Siliconix P-Channel Enhancement-Mode Transistors Product Summary P a rt N um ber V BR DSS (V) r DS(on) ( ß ) I d (A) IRFD9120 -100 0.60 - 1 .0 IRFD9123 -6 0 0.80 -0.8 S o 4-Pin DIP G 0 - 1|— HE • u Top View D D P-C hannel M O S F E T

GAL22V10C-10LJI

Abstract: GAL22V10C-5LJ GAL22V10 GAL22V10B-7LJ GAL22V10B-7LP GAL22V10C GAL22V10C-7LJ GAL22V10C-7LP GAL22V10B-15LJ GAL22V10C-10LP
Contextual Info: Specifications GAL22V10 GAL22V10 High Performance E2CMOS PLD Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM 2 • HIGH PERFORMANCE E CMOS TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 200 MHz — 4 ns Maximum from Clock Input to Data Output

P281 B01

Abstract: G187
Contextual Info: LogiCORE IP Processing System 7 v4.02a DS871 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The Processing System 7 IP is the software interface around the Zynq Processing System. The Zynq -7000 family consists of an system-on-chip (SoC) style

Contextual Info: User’s Manual The sales of these products are limited for China, Hong Kong, and India. R7F0C008A/B/F, R7F0C009A/B/F 16 User’s Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications,

16R8

Abstract: GAL16LV8ZD GAL16LV8ZD-15QJ GAL16LV8ZD-25QJ GAL16V8
Contextual Info: Specifications GAL16LV8ZD GAL16LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

Contextual Info: Specifications GAL6001 GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay

7486 XOR GATE

Abstract: circuit diagram of half adder using IC 7486 7486 2-input xor gate ic 7486 XOR GATE pin configuration IC 7486 pin configuration of 7486 IC vhdl code for vending machine pin DIAGRAM OF IC 7486 data sheet IC 7408 laf 0001
Contextual Info: Lattice Semiconductor Handbook 1994 Click on one of the following choices: • Table of Contents • How to Use This Handbook • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Handbook 1994 i Copyright © 1994 Lattice Semiconductor Corporation.

PLSI 1016-60LJ

Abstract: PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT
Contextual Info: Lattice Semiconductor Data Book 1996 Click on one of the following choices: • Table of Contents • Data Book Updates & New Products • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. ispLSI and pLSI Product Index Pins Density

isp1032

Abstract: lattice 1032-60LJ 1032E-8
Contextual Info: Specifications ispLSI and pLSI 1032 ispLSI and pLSI 1032 ® High-Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs

P36E

Abstract: UDFN-08 CM1636 CM1636-04DE CM1636-08DE UDFN-16 UDFN-8 Land Pattern
Contextual Info: PRELIMINARY CM1636 4, 6 and 8 Channel EMI Filter Arrays with ESD Protection Features Product Description • California Micro Devices's CM1636 is an EMI filter array with ESD protection, which integrates either four, six or eight pi filters C-R-C . Each CM1636 filter has

GAL 0042b

Abstract: 1032E
Contextual Info: ® ispLSI and pLSI 1032E High-Density Programmable Logic • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs

1048C

Abstract: cpga 476 1048C50LQI 1048C-70
Contextual Info: Specifications ispLSI and pLSI 1048C ® ispLSI and pLSI 1048C High-Density Programmable Logic Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers

isp1024

Abstract: PLSI 1024-60LJ lattice 1024-60LJ isplsi device layout
Contextual Info: Specifications ispLSI and pLSI 1024 ® ispLSI and pLSI 1024 High-Density Programmable Logic Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs — 144 Registers

2032LV

Abstract: TMS3534
Contextual Info: ispLSI 2032V/LV 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 7.5 ns Propagation Delay A1 A2 D Q GLB A6 D Q D Q A5 D Q A3 A4

GAL6002

Abstract: MAX235
Contextual Info: GAL 6002: 4-to-1 RS232 Port Multiplexer Figure 1. TxD During Single Byte Transfer Introduction The GAL6002 is the most versatile 24-pin PLD available today. Its FPLA architecture offers buried macrocells, D/E registers, programmable clocks and dedicated input

an8017

Contextual Info: Phase Locked Loops PLL in High-Speed Designs to generate the desired output frequency. Figure 1 is a block diagram of a simple PLL circuit. Introduction This application note describes the construction of a Phase Detector (PD) in conjunction with a Voltage Controlled Oscillator (VCO) to create a frequency generator

16V8D

Abstract: 16V8 GAL16V8 GAL16V8C-5LJ GAL16V8C-5LP GAL16V8C-7LP GAL16V8D-3LJ GAL16V8D-5LJ GAL16V8D-7LJ GAL16V8D-7LP
Contextual Info: GAL16V8 High Performance E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES 2 • HIGH PERFORMANCE E CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.0 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology

conversion software jedec lattice

Abstract: isp Cable lattice sun
Contextual Info: TM ISP Daisy Chain Download Software system quickly and easily. Most importantly, devices can be programmed again and again, depending on your system needs. Features • LATTICE SEMICONDUCTOR CORPORATION LSC) SOFTWARE FOR IN-SYSTEM PROGRAMMING In-System Programmability

Contextual Info: ispLSI and pLSI 2064V ® High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 and 32 I/O Pin Versions, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State