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    ON ERROR CORRECTION CODE IN FPGA IN VHD Search Results

    ON ERROR CORRECTION CODE IN FPGA IN VHD Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    5446/BEA
    		Rochester Electronics LLC 5446 - Decoder, BCD-To-7-Segment, With Open-Collector Outputs - Dual marked (M38510/01006BEA) PDF Buy
    54LS190/BEA
    		Rochester Electronics LLC 54LS190 - BCD Counter, 4-Bit Synchronous Up/Down, With Mode Control - Dual marked (M38510/31513BEA) PDF Buy
    54LS224AJ/B
    		Rochester Electronics LLC 54LS224 - 64-Bit FIFO Memories PDF Buy
    AV-THLIN2BNCM-007.5
    		Amphenol Cables on Demand Amphenol AV-THLIN2BNCM-007.5 Thin-line Coaxial Cable - BNC Male / BNC Male (SDI Compatible) 7.5ft PDF
    CN-DSUB25SKT0-000
    		Amphenol Cables on Demand Amphenol CN-DSUB25SKT0-000 D-Subminiature (DB25 Female D-Sub) Connector, 25-Position Socket Contacts, Solder-Cup Terminals PDF

    ON ERROR CORRECTION CODE IN FPGA IN VHD Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    XIP2173

    Abstract: DCM-1 dcm11 error correction code in vhdl verilog implementation of error correcting code application of optical encoder Reed-Solomon Decoder verilog code XC2V500-5 CC345
    Contextual Info: G.709-Compliant FEC Core CC345 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc345.ucf Testbench, test scripts Verification Tool Instantiation Templates


    Original     		709-Compliant CC345) cc345 XIP2173 DCM-1 dcm11 error correction code in vhdl verilog implementation of error correcting code application of optical encoder Reed-Solomon Decoder verilog code XC2V500-5 PDF

    atm header error checking

    Abstract: Cell phone schematic circuit atm header-error-check multiple bit cell phone CRC-10 CRC-32 PC84 XC4000XL LCD module in VHDL error correction code in vhdl
    Contextual Info: Cell Delineation CC-200 January 26, 1998 C ooreEl MicroSystems CoreEl MicroSystems 46750 Fremont Blvd. #208 Fremont, CA 94538 USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 URL: www.coreel.com E-mail: sales@coreel.com Features • • • • • • •


    Original     		CC-200) atm header error checking Cell phone schematic circuit atm header-error-check multiple bit cell phone CRC-10 CRC-32 PC84 XC4000XL LCD module in VHDL error correction code in vhdl PDF

    RAMB18E1

    Abstract: FIFO36E1 FIFO18E1 RAMB36E1 RAMB36SDP FIFO18 RAMB18SDP RAMB36E1 read back Virtex-5 Ethernet development fifo vhdl
    Contextual Info: Virtex-6 FPGA Memory Resources User Guide UG363 v1.3.1 January 19, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG363 64-bit 72-bit RAMB18E1 FIFO36E1 FIFO18E1 RAMB36E1 RAMB36SDP FIFO18 RAMB18SDP RAMB36E1 read back Virtex-5 Ethernet development fifo vhdl PDF

    design of scrambler and descrambler

    Abstract: vhdl code scrambler verilog code for implementation of des error correction code in vhdl vhdl code for phase shift Descrambler vhdl code for scrambler descrambler cell phone vhdl code for pseudo random sequence generator crc 16 verilog
    Contextual Info: DSD Distributed Sample Descrambler January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features


    Original     		I-10148 53-bit design of scrambler and descrambler vhdl code scrambler verilog code for implementation of des error correction code in vhdl vhdl code for phase shift Descrambler vhdl code for scrambler descrambler cell phone vhdl code for pseudo random sequence generator crc 16 verilog PDF

    XAPP864

    Abstract: verilog hdl code for triple modular redundancy ML507 xilinx uart verilog code for spartan 3a frame_ecc ML505 RAM SEU Xilinx VIRTEX-5 xc5vlx50 ug191 uart verilog testbench
    Contextual Info: Application Note: Virtex-5 Family SEU Strategies for Virtex-5 Devices Author: Ken Chapman XAPP864 v2.0 April 1, 2010 Summary Xilinx devices are designed to have an inherently low susceptibility to single event upsets (SEUs). This application note provides a substantial discussion of strategies and


    Original     		XAPP864 XAPP864 verilog hdl code for triple modular redundancy ML507 xilinx uart verilog code for spartan 3a frame_ecc ML505 RAM SEU Xilinx VIRTEX-5 xc5vlx50 ug191 uart verilog testbench PDF

    CI 4011

    Abstract: L64713 datasheet ci 4011 L64711 L64712 gf multiplier vhdl program ANRS13 AHA4011 AHA4013 L6471
    Contextual Info: aha products group AHA Application Note Converting from LSI Logic's L647xx device to AHA4011/12/13 ANRS13_0404 Comtech EF Data Corporation 1126 Alturas Drive Moscow ID 83843 tel: 208.892.5600 fax: 208.892.5601 www.aha.com aha products group Table of Contents


    Original     		L647xx AHA4011/12/13 ANRS13 AHA4011/12/13 CI 4011 L64713 datasheet ci 4011 L64711 L64712 gf multiplier vhdl program AHA4011 AHA4013 L6471 PDF

    XILINX vhdl code REED SOLOMON encoder decoder

    Abstract: Reed-Solomon Decoder verilog code verilog code for digital calculator XILINX vhdl code download REED SOLOMON Reed-Solomon Decoder XILINX vhdl code REED SOLOMON 941-740 Solomon vhdl code download REED SOLOMON viterbi convolution
    Contextual Info: Reed-Solomon Decoder January 10, 2000 Product Specification AllianceCORE Facts Integrated Silicon Systems, Ltd. 50 Malone Rd Belfast BT9 5BS Northern Ireland Phone: +44 1232 664664 Fax: +44 1232 669664 E-Mail: info@iss-dsp.com URL: www.iss-dsp.com Features


    Original     		4000X, XILINX vhdl code REED SOLOMON encoder decoder Reed-Solomon Decoder verilog code verilog code for digital calculator XILINX vhdl code download REED SOLOMON Reed-Solomon Decoder XILINX vhdl code REED SOLOMON 941-740 Solomon vhdl code download REED SOLOMON viterbi convolution PDF

    XILINX vhdl code REED SOLOMON

    Abstract: XILINX vhdl code REED SOLOMON encoder decoder vhdl code download REED SOLOMON vhdl code for interleaver XILINX vhdl code download REED SOLOMON 02HEX XC4000XL Schematic convolution interleaving viterbi convolution
    Contextual Info: Reed-Solomon Decoder January 26, 1998 Product Specification AllianceCORE Facts Integrated Silicon Systems, Ltd. 50 Malone Rd Belfast BT9 5BS Northern Ireland Phone: +44 1232 664664 Fax: +44 1232 669664 E-Mail: info@iss-dsp.com URL: www.iss-dsp.com Features


    Original     		PDF

    vhdl code hamming

    Abstract: vhdl coding for hamming code vhdl code for pipelined matrix multiplication vhdl code for matrix multiplication vhdl code hamming ecc parity ECC SEC-DED Hamming code SRAM verilog code for matrix multiplication SECDED RTAX2000S vhdl code SECDED
    Contextual Info: Application Note AC273 Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs Applies to EDAC Core from Libero IDE v7.1 or Older Introduction Actel's newest designed-for-space Field Programmable Gate Array FPGA family, the RTAX-S, is a highperformance, high-density antifuse-based FPGA with embedded user static RAM (SRAM). Based on Actel's


    Original     		AC273 l011011101101 vhdl code hamming vhdl coding for hamming code vhdl code for pipelined matrix multiplication vhdl code for matrix multiplication vhdl code hamming ecc parity ECC SEC-DED Hamming code SRAM verilog code for matrix multiplication SECDED RTAX2000S vhdl code SECDED PDF

    CTXIL206

    Abstract: vhdl code for multiplexing MPEG2 sd card interfacing spartan 3E FPGA RX 3E vhdl code for multiplexing table dvb-t XAPP1015 vhdl code for spartan 6 audio vhdl code for multiplexing Tables in dvb-t vhdl code for dvb-t 2 YCbCr output LVDS
    Contextual Info: Audio/Video Connectivity Solutions for Spartan-3E FPGAs Reference Designs for the Broadcast the Broadcast Industry: Volume 3 Industry: Volume 3 [optional] XAPP1015 v1.0 September 28, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original     		XAPP1015 CTXIL206 vhdl code for multiplexing MPEG2 sd card interfacing spartan 3E FPGA RX 3E vhdl code for multiplexing table dvb-t XAPP1015 vhdl code for spartan 6 audio vhdl code for multiplexing Tables in dvb-t vhdl code for dvb-t 2 YCbCr output LVDS PDF

    vhdl code scrambler

    Abstract: scrambling design of scrambler and descrambler verilog code for implementation of des error correction code in vhdl vhdl code Linear block code Scrambler vhdl code for pseudo random sequence generator crc 16 verilog vhdl code CRC 32
    Contextual Info: DSS Distributed Sample Scrambler January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and


    Original     		I-10148 vhdl code scrambler scrambling design of scrambler and descrambler verilog code for implementation of des error correction code in vhdl vhdl code Linear block code Scrambler vhdl code for pseudo random sequence generator crc 16 verilog vhdl code CRC 32 PDF

    XAPP1014

    Abstract: smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits
    Contextual Info: Audio/Video Connectivity Solutions for Virtex-5 FPGAs Reference Designs for the Broadcast Industry: Volume 2 XAPP1014 v1.2 November 9, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original     		XAPP1014 XAPP1014 smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits PDF

    fpga vhdl code for crc-32

    Contextual Info: Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices AN-539-2.0 Application Note This application note describes how to use the enhanced error detection cyclic redundancy check CRC feature in the Arria II, Stratix III, Stratix IV, Stratix V, and


    Original     		AN-539-2 fpga vhdl code for crc-32 PDF

    CC226

    Abstract: simple powerful charge controller block diagram vhdl code for 8-bit calculator register based fifo xilinx crc verilog code 16 bit vhdl code for scrambler descrambler CRC-16 CRC-32 rx data path interface in vhdl vhdl code CRC32
    Contextual Info: CoreEl 2.5 Gb/s GFP Framer CC226 May 30, 2003 Product Specification AllianceCORE™ Facts Core Specifics See Table 1 Provided with Core Documentation Functional Specification Design File Formats EDIF netlist Constraints File .ucf Script Based Behavioral


    Original     		CC226) CC226 simple powerful charge controller block diagram vhdl code for 8-bit calculator register based fifo xilinx crc verilog code 16 bit vhdl code for scrambler descrambler CRC-16 CRC-32 rx data path interface in vhdl vhdl code CRC32 PDF

    UG386

    Abstract: SPARTAN-6 GTP XC6SLX25 XC6SLX75T CSG324 MGTRXP0 XC6SL XC6SLX25T CSG484 DSP48A1
    Contextual Info: Spartan-6 FPGA GTP Transceivers Advance Product Specification UG386 v2.2 April 30, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG386 UG386 SPARTAN-6 GTP XC6SLX25 XC6SLX75T CSG324 MGTRXP0 XC6SL XC6SLX25T CSG484 DSP48A1 PDF

    UG196

    Abstract: MP21608S221A xc5vlx30t-ff323 XC5VLX155T-FF1738 XC5VSX50TFF665 direct sequence spread spectrum virtex-5 FERRITE-220 FF1136 XC5VLX30T-FF665 XC5VLX110T-FF1738
    Contextual Info: Virtex-5 FPGA RocketIO GTP Transceiver User Guide UG196 v2.1 December 3, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG196 time16 UG196 MP21608S221A xc5vlx30t-ff323 XC5VLX155T-FF1738 XC5VSX50TFF665 direct sequence spread spectrum virtex-5 FERRITE-220 FF1136 XC5VLX30T-FF665 XC5VLX110T-FF1738 PDF

    CRC-16 and verilog

    Abstract: vhdl code scrambler CRC-16 CRC-32 OTN SWITCH header G.7041 GFP XC2V500-5 CRC-16 and CRC-32 Ethernet
    Contextual Info: CoreEl 8-Bit Multichannel GFP Framer CC225 May 30, 2003 Product Specification AllianceCORE™ Facts Core Specifics See Table 1 Provided with Core Documentation CC225 Functional Specification Design File Formats EDIF netlist Constraints File .ucf Script Based Behavioral


    Original     		CC225) CC225 apCC225 CRC-16 and verilog vhdl code scrambler CRC-16 CRC-32 OTN SWITCH header G.7041 GFP XC2V500-5 CRC-16 and CRC-32 Ethernet PDF

    fpga vhdl code for crc-32

    Abstract: crc verilog code 16 bit verilog code for 10 gb ethernet verilog code for frame synchronization sonet testbench XC2VP20 vhdl code scrambler STM 64 FRAMER WITH OTN vhdl code stm-64 CRC-16
    Contextual Info: CoreEl CC327 10Gb GFP Framer May 6, 2003 Product Specification AllianceCORE™ Facts Paxonet Communications, Inc. 4046 Clipper Court Fremont CA 94538, USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 E-mail: sales@paxonet.com URL: www.paxonet.com Features


    Original     		CC327 OC-192 fpga vhdl code for crc-32 crc verilog code 16 bit verilog code for 10 gb ethernet verilog code for frame synchronization sonet testbench XC2VP20 vhdl code scrambler STM 64 FRAMER WITH OTN vhdl code stm-64 CRC-16 PDF

    UG366

    Abstract: XC6VLX75T-FF784 aurora GTX XC6VLX240T-FF1759 verilog code of prbs pattern generator XC6VLX130T-FF784 XC6VSX475T-FF XC6VLX240T-FF784 XC6VLX130T FF1156
    Contextual Info: Virtex-6 FPGA GTX Transceivers User Guide UG366 v2.2 February 23, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG366 UG366 XC6VLX75T-FF784 aurora GTX XC6VLX240T-FF1759 verilog code of prbs pattern generator XC6VLX130T-FF784 XC6VSX475T-FF XC6VLX240T-FF784 XC6VLX130T FF1156 PDF

    7 Series FPGAs GTP Transceivers User Guide, UG482 v1.5

    Contextual Info: 7 Series FPGAs GTP Transceivers User Guide UG482 v1.6 August 28, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL


    Original     		UG482 7 Series FPGAs GTP Transceivers User Guide, UG482 v1.5 PDF

    vhdl code for phase frequency detector

    Abstract: vhdl code for phase frequency detector for FPGA maxim vco XAPP250 verilog code for phase detector XAPP224 DATA RECOVERY wolaver x250040 vhdl code for DCO phase detector
    Contextual Info: Application Note: Virtex-II Family Clock and Data Recovery with Coded Data Streams R Author: Leonard Dieguez XAPP250 v1.3.2 May 2, 2007 Summary This application note and reference design outline a method to implement clock and data recovery in Virtex -II devices. Although not limiting the implementation to a specific FPGA


    Original     		XAPP250 8B/10B XAPP224. app979, vhdl code for phase frequency detector vhdl code for phase frequency detector for FPGA maxim vco XAPP250 verilog code for phase detector XAPP224 DATA RECOVERY wolaver x250040 vhdl code for DCO phase detector PDF

    ug198

    Abstract: XC5VFX130T-FF1738 XC5VFX30T-FF665 XC5VFX70T-FF665 MGTRXP0 MP21608S221A RocketIO seminar Applications Book Maxim VCO 10G vhdl code for 16 prbs generator
    Contextual Info: Virtex-5 FPGA RocketIO GTX Transceiver User Guide UG198 v3.0 October 30, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG198 time62 ug198 XC5VFX130T-FF1738 XC5VFX30T-FF665 XC5VFX70T-FF665 MGTRXP0 MP21608S221A RocketIO seminar Applications Book Maxim VCO 10G vhdl code for 16 prbs generator PDF

    verilog hdl code for matrix multiplication

    Abstract: vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code
    Contextual Info: Application Note AC319 Using EDAC RAM for RadTolerant RTAX-S/SL and Axcelerator FPGAs Applies to EDAC Core from Libero IDE v7.2 and Newer Introduction The newest Actel designed-for-space field programmable gate array FPGA family, RTAX-S/SL, is a highperformance, high-density, antifuse-based FPGA with embedded user static RAM (SRAM). Based on the


    Original     		AC319 verilog hdl code for matrix multiplication vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code PDF

    XILINX vhdl code REED SOLOMON encoder decoder

    Abstract: "Galois Field Multiplier" verilog Reed-Solomon Decoder verilog code XILINX vhdl code download REED SOLOMON encoder decoder XILINX vhdl code download REED SOLOMON vhdl code for 8-bit parity generator vhdl code for a 9 bit parity generator convolution encoder datasheet Reed-Solomon Decoder viterbi convolution
    Contextual Info: Reed-Solomon Encoder January 10, 2000 Product Specification AllianceCORE Facts Integrated Silicon Systems, Ltd. 50 Malone Rd Belfast BT9 5BS Northern Ireland Phone: +44 1232 664664 Fax: +44 1232 669664 E-Mail: info@iss-dsp.com URL: www.iss-dsp.com Features


    Original     		4000X, XILINX vhdl code REED SOLOMON encoder decoder "Galois Field Multiplier" verilog Reed-Solomon Decoder verilog code XILINX vhdl code download REED SOLOMON encoder decoder XILINX vhdl code download REED SOLOMON vhdl code for 8-bit parity generator vhdl code for a 9 bit parity generator convolution encoder datasheet Reed-Solomon Decoder viterbi convolution PDF