O227 Search Results

Contextual Info: ^ jjjjjy .•/$ $$$$I ♦ PRELIMINARY < ij /t t5;*^ ' CY37512 UltraLogic 512-Macrocell ISR™ CPLD — tco = 6 ns Features • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ (ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

5d3 diode

Abstract: 6B15 7b12 MACH Programmer transistor 7B12 2D15 PAL 007 A power generator control circuit schematic 1C12 5D10
Contextual Info: MACH 5 CPLD Family I MAC ncludes H Adv anc 5A Fam e In form ily atio n Fifth Generation MACH Architecture FEATURES ◆ High logic densities and I/Os for increased logic integration ◆ ◆ ◆ ◆ ◆ ◆ ◆ — 128 to 512 macrocell densities — 68 to 256 I/Os

ic 4040

Abstract: 4040 cmos ci 4040 cmos 4040 stv 4325 O129-O135 PD16707 4040
Contextual Info: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社

Contextual Info: 1 MACH 5 FAMILY MACH 5 Family Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ Publication# 20446 Amendment/0 Rev: D Issue Date: August 1997 MACH 5 Family ◆ Fifth generation MACH architecture — 100% routable

CY37512

Abstract: CY37512V
Contextual Info: Back PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

clcc land pattern

Abstract: CY37512VP208-66UMB CY37032VP44-100AI CY37064P44-154YMB CY37256P160-125UMB TO-220AB/clcc land pattern
Contextual Info: CYPRESS PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs General Description Features • In-System Reprogram mable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

gck451

Abstract: 2818C AT40K AT40K05AL AT40K10AL AT40K20AL AT40K40AL AT40KAL XC4000 XC5200
Contextual Info: Features • Ultra High Performance • • • • • • • • • • – System Speeds to 100 MHz – Array Multipliers > 50 MHz – 10 ns Flexible SRAM – Internal Tri-state Capability in Each Cell FreeRAM – Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM

max 8770

Abstract: MOS 6526 SR299 diode 3562 SR300 IC 6994 14 pin SR300 datasheet what is product ON 4914
Contextual Info: PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT µ PD16708 300-OUTPUT TFT-LCD GATE DRIVER DESCRIPTION The µ PD16708 is a TFT-LCD gate driver equipped with 300-output lines. It can output a high-gate scanning voltage in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit.

O2-A2

Abstract: Lattice Mach OX2 VCCIO11 ispMACH M4A3 M4A5-192 application note PAL 007 O64i
Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

blm21p221sn

Abstract: MICTOR38P RJ45INTLED S29GL128M10TFIR1 db9rf 1N4001SM k163 0U001 BLM21P221 k168
Contextual Info: 5 Page 16 4 Mictor Connector pld_MICTORCLK TCK TMS TDO TDI TRST TR_CLK MICTOR[24:0] Page 3-5 pld_MICTORCLK TCK TMS TDO TDI TRST TR_CLK MICTOR[24:0] ADC D adc_PLLCLK1 adc_PLLCLK2 adc_CLK_IN1 adc_CLK_IN1_n adc_CLK_IN2 adc_CLK_IN2_n adcA_D[11:0] adcB_D[11:0]

CY37512P208-100UMB

Abstract: CY37512P208-100UM CY37032VP44-100AI CY37256P160-83UM CY37064P44-154YMB CY37256P160-125UMB CERAMIC leaded CHIP CARRIER CLCC 68
Contextual Info: Family PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37032VP44-100AI

Abstract: CY37064P44-154YMB CY37512P208-100UMB
Contextual Info: Family Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

QML-38535

Abstract: AT40KFL040 5962-0325002QXC o26f at40kfl040kz1sv
Contextual Info: REVISIONS LTR DESCRIPTION A B DATE YR-MO-DA APPROVED Added asynchronous timing waveform to figure 3. Updated boilerplate. ksr 04-07-04 Raymond Monnin Add device type 02 which is a 5 volt tolerant version. Editorial changes throughout. tcr 06-06-27 Raymond Monnin

74287

Abstract: ML9461B
Contextual Info: FEDL9461-01 Issue Date: Jan 29, 2009 ML9461B Segment Driver for Dot Matrix STN Liquid Crystal Display 1. Product Overview 1.1 General Description The ML9461B is a 320-output segment driver for driving a dot matrix LCD panel. The driver enables switching between 320 outputs and 240 outputs and 200 outputs. The ML9461B is used in

RXIL 2

Abstract: RTXP 18 ASEA asea relay RI RXIL24 asea time-lag relay RI RXIDE ASEA SK 661 asea eg 315 ASEA motors RTXP18 ASEA
Contextual Info: ASEA Catalogue RK 65-14 E Edition 1 June 1975 FJIeR, P a rtí Two-phase instantaneous overcurrent protective relays • used prim a rily as s h o rt-c irc u it pro­ te ctio n in isolated systems, e.g. for m otors. • static o r electrom e chan ica l current

o12n3

Abstract: DF Series MN863830EFH O237 O227
Contextual Info: STN LCD Driver MN863830EFH 240-Output STN Segment Driver • Overview The MN863830EFH is a 240-output segment driver IC for dot matrix STN LCD panels. It latches 8-bit or 12-bit parallel data transferred from an LCD controller and generates the LCD drive signals.

O2-A2

Abstract: C10C8
Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

tico 732

Abstract: TEA1012 CALIFORNIA MICRO DEVICES catalog O2 micro
Contextual Info: PRELIMINARY The MACH 5 Family Fifth Generation MACH Architecture V A N T I S The Programmable Logic Company From AMD DISTINCTIVE CHARACTERISTICS • Fifth generation MACH architecture — 100% routable — 5-V devices will not overdrive 3-V inputs safe for

O318

Abstract: MN86372 MN863831EFS 40-stage o306 ilo3
Contextual Info: STN LCD Driver MN863831EFS 320-Output STN Segment Driver • Overview The MN863831EFS is a 320-output segment driver IC for dot matrix STN LCD panels. It latches 4-bit or 8-bit parallel data transferred from an LCD controller and generates the LCD drive signals.

TQFP-144 footprint

Abstract: AT40K AT40K05AL AT40K10AL AT40K20AL AT40K40AL AT40KAL XC4000 XC5200 PQFP 352
Contextual Info: Features • Ultra High Performance • • • • • • • • • – System Speeds to 100 MHz – Array Multipliers > 50 MHz – 10 ns Flexible SRAM – Internal Tri-state Capability in Each Cell FreeRAM – Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM

at40k20al-1bqu

Abstract: AT40K40AL-1BQU AT40K05AL AT40K10AL AT40K20AL AT40K40AL AT40KAL XC4000 XC5200 AT40K
Contextual Info: Features • Ultra High Performance • • • • • • • • • • – System Speeds to 100 MHz – Array Multipliers > 50 MHz – 10 ns Flexible SRAM – Internal Tri-state Capability in Each Cell FreeRAM – Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM

n20s

Abstract: CY3600 CY37512 CY37512V 0228l
Contextual Info: C Y37512 PR ELIMINA RY UltraLogic 512-Macrocell ISR™ CPLD — tc o = 6 ns Features • P ro d uct-term clocking • 512 m a cro c ells in 32 logic blo cks • IEEE 1149.1 JTAG b o u n d a ry scan • In-S ystem R ep ro g ra m m ab le ™ IS R ™ • P ro g ram m ab le slew rate control on ind ividu al l/O s

ic tlp 251

Abstract: tlp 071 o240 CY37512 CY37512V
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ .-” ^ •■■■■■■ ^ 'S f c jjÉBT *¿f5’00“’’*<'^1; .r7“T{• PRELIMINARY CY37512V i k v/ k#> UltraLogic 3.3V 512-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming

512256

Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature