MT4C4001JDJ Search Results

Contextual Info: |U |IC=RO N 2 MEG DRAM MODULE X MT18D236 36 DRAM MODULE 2 MEG x 36 DRAM FAST PAGE MODE FEATURES • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance, CMOS silicon-gate process. • Single 5V ±10% power supply • All device pins are fully TTL compatible

Contextual Info: MT6D118 1 MEG X 18 DRAM MODULE M IC R O N 1 MEG X 18 DRAM FAST PAGE MODE FEATURES • Industry standard pinout in a 72-pin single-in-line package • High-performance, CMOS silicon-gate process • Single 5V ±10% power supply • All device pins are fully TTL compatible

MT18D236

Contextual Info: |U|K=RON 2 MEG DRAM MODULE 2 MEG X MT18D236 36 DRAM MODULE X 36 DRAM FAST-PAGE-MODE FEATURES • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance CMOS silicon-gate process. • Single 5V ±10% power supply • All device pins are TTL-compatible

Contextual Info: fUIICRON DRAM _ . . - . _ _ Ä 1 MEG X 8 1 MEG x 8 FAST-PAGE-MODE _ MT2D18 DRAM MODULE d ra m MT2D18 LOW POWER, FY T F M n P n RF EXTENDED REFRESH (MT2D18 L) M O D U LE • ■ I V / 1 ^ W ^ I— FEATURES • Industry-standard pinout in a 30-pin, single-in-line

MT4C4001

Contextual Info: MT20D240 2 MEG X 40 DRAM M ODULE p iC R O fS J 2 MEG X 40 DRAM DRAM MODULE NEW I FAST PAGE MODE MT20D240 LOW POWER, EXTENDED REFRESH (MT20D240 L) FEATURES • • • • PIN ASSIGNMENT (Top View) 72-pin single-in-line package High-performance CM OS silicon-gate process.

Contextual Info: |U |IC R O N lEG X 1 MEG DRAM MODULE MT6D118 18 DRAM MODULE X 18 DRAM FAST-PAGE-MODE FEATURES PIN ASSIGNMENT Top View • Industry-standard pinout in a 72-pin single-in-line package • High-performance CM OS silicon-gate process • Single 5V ±10% power supply

T3D19

Abstract: 30-pin simm memory "16m x 8" MT4C1024DJ MT3019 MT4C4001 30-pin SIMM
Contextual Info: [M IC R O N 1 MEG X MT3D19 9 DRAM MODULE 1 MEG x 9 DRAM DRAM MODULE FAST PAGE MODE MT3D19 LOW POWER, EXTENDED REFRESH (MT3D19 L) FEATURES PIN ASSIGNMENT (Top View) • Industry standard pinout in a 30-pin single-in-line memory module • High-performance, CM OS silicon-gate process

MT18D236

Contextual Info: [MICRON 2 MEG DRAM MODULE X MT18D236 36 DRAM MODULE 2 MEG X 36 DRAM FAST-PAGE-MODE FEATURES PIN A SSIG N M EN T Top View • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance CM OS silicon-gate process. • Single 5V ±10% power supply

t3d19

Abstract: MT4C1024DJ a7020
Contextual Info: [MICRON □PAM _ _ _ _ . . _ 1 MEG X MT3D19 9 DRAM MODULE 1 MEG x 9 DRAM _ FAST-PAGE-MODE MT3D19 LOW POWER, EXTENDED REFRESH (M T3D19 L) MODULE \J L. t . IVIv y U FEATURES PIN ASSIGNMENT (Top View) • Industry-standard pinout in a 30-pin single-in-line

FPM DRAM 30-pin SIMM

Abstract: T2D18
Contextual Info: I^ IIC n D N lEG DRAM MODULE X 8 MT2D18 DRAM MODULE 1 MEG x 8 1 MEGABYTE, 5V, FAST PAGE MODE FEATURES • JEDEC- and industry-standard pinout in a 30-pin, single-in-line m emory m odule SIMM • High-perform ance CM OS silicon-gate process • Single 5V ±10% power supply

MT4C4007JDJ

Abstract: ST bsx 26
Contextual Info: MTHat3Z XI(SFr MTt6D222(XJ (S | t M B G *ZM EE jc3ZDRÄIW1 M O D ULE DRAM 1 MEG, 2 MEG x 32 M UW D U L tr - 4, 8 MEGABYTE, 5V, OPTIONAL SELF REFRESH, FAST PAGE OR EDO PAGE MOPE FEATURES • JE D E C - a n d i n d u s tr y - s ta n d a r d pinout in a 72-pin,

Contextual Info: MICR ON S E M I C O N D U C T O R INC b3E D • b l l l S M T D D D V bb ? 51b ■ MRN MT4C4004J 1 MEG x 4 DRAM I^HCRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST-PAGE-MODE FEATURES _ PIN ASSIGNMENT Top View • Four independent CAS controls, allowing individual

Contextual Info: M ICRON SEM ICONDUCTOR INC b3E D M IC R O N WÊ b lllS M T 1 MEG X 0 G D 7 cì b G b O 1» « P I R N MT3D19 9 DRAM MODULE 1 MEG X 9 DRAM DRAM MODULE FAST-PAGE-MODE MT3D19 LOW POWER, EXTENDED REFRESH (MT3D19 L) FEATURES • Industry-standard pinout in a 30-pin single-in-line

Contextual Info: MICRON □ P A 2 MEG M M 2 _ M T16D 232 32, 4 MEG x 16 DRAM M O D ULE X E G x 3 2 > M 4 E G x 1 6 FAST PAGE MODE (MT16D232 LOW POWER, FXTFNDFD EXTENDED RF REFRESH (MT16D232 L) M O D U LE I V I V / U U L .I— FEATURES PIN ASSIGNMENT (Top View) OPTIONS 72-Pin SIMM

Contextual Info: MT4C4001 J L 1 MEG X 4 DRAM (M IC R O N DRAM 1 MEG x 4 DRAM DRAM STANDARD OR LOW POWER, EXTENDED REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J L) • Industry-standard x4 pinout, timing, functions and packages

T2D19

Contextual Info: M IC R O N MT2D18 1 MEG X 8 DRAM MODULE I 1 MEG X 8 DRAM DRAM MODULE FAST PAGE MODE FEATURES OPTIONS MARKING Timing 60ns access 70ns access 80ns access -6 -7 -8 Packages Leadless 30-pin SIMM M Part Number Example: MT2D18M-6 PIN ASSIGNMENT Top View 30-Pin SIMM

Contextual Info: MT4C4004J 1 MEG X 4 DRAM |U|IC=RON DRAM 1 MEG x 4 DRAM FEATURES _ • Four independent CAS controls, allowing individual manipulation to each of the four data input/output ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words when using 1 Meg x 4 DRAMs for memory

Contextual Info: MT4C4001 J S 1 MEG X 4 DRAM (MICRON DRAM 1 MEG x 4 DRAM 5V, STANDARD OR SELF REFRESH • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM OS silicon-gate process

Contextual Info: M IC R O N I DRAM . « . Ä MT24D236 2 MEG X 36, 4 MEG X 18 DRAM MODULE 2 MEG x 36>4 MEG x 18 « FAST PAGE MODE MT24D236 LOW POWER, P EXTENDED Y T P M n p n R REFRESH F (MT24D236 L) MODULE I V I v U v L L FEATURES • Industry-standard pinout in a 72-pin single-in-line

T3D19

Contextual Info: |V|IC =R O N 1 MEG DRAM MODULE 1 MEG X X M T3D19 9 DRAM M O D ULE 9 DRAM FAST-PAGE-MODE MT3D19 LOW POWER, EXTENDED REFRESH (MT3D19 L) FEATURES • Industry-standard pinout in a 30-pin single-in-line memory module • High-performance CMOS silicon-gate process

T2D18

Contextual Info: I^ IIC R O IS I 1 MEG 1 MEG DRAM MODULE X X MT2D18 8 DRAM M ODULE 8 DRAM FAST PAGE MODE FEATURES • Industry-standard pinout in a 30-pin, single-in-line memory module • High-perform ance CM OS silicon-gate process • Single 5V +10% power supply • Low power, 6mW standby; 450mW active, typical

MT18D236G6

Contextual Info: l^ iic n o N 2 MEG X MT18D236 36 DRAM MODULE 2 MEG X 36 DRAM DRAM MODULE FAST PAGE MODE FEATURES • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance, CM OS silicon-gate process. • Single 5V ±10% power supply • All device pins are fully TTL compatible

T4C400

Abstract: mt4c4004jdj
Contextual Info: M T4C4004J 1 MEG X 4 DRAM l^ldRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST PAGE MODE FEATURES _ • Four independent C A S controls, allo w ing in d ivid u al m anipulation to each of the four data In p u t/O u tp ut ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words w hen using 1 M eg x 4 D R A M s for m emory

marking JE 6 pin

Contextual Info: [MICRON 1 MEG DRAM MODULE X 1 MEG MT6D118 18 DRAM MODULE X 18 DRAM NEW I FAST PAGE MODE FEATURES OPTIONS PIN ASSIGNMENT Top View 72-Pin SIMM (T-16) M T 6 D 1 1 8 M /G MARKING • Timing 60ns access 70ns access 80ns access 6 - 7 - Packages Leadless 7 2 -pin SIMM