MS-012-AB
Abstract: MS-012AB MS-012AB Package MS-012AA MS-012AC
Contextual Info: Q QUALITY SEMICONDUCTOR, INC. Selection Guide and Packaging Information 150-MIL SOIC - Package Code S1 Plastic Small Outline Gull-Wing 1 E H N D SEATING PLANE A B e JEDEC# h x 45° L α A1 MS-012AA MS-012AB C MS-012AC Symbol Min Nom Max Min Nom Max Min Nom
|
Original
|
150-milms-012aams-012abms-012ac+2ms-012-abms-012ab package
|
PDF
|
MS-012-AB
Abstract: 14P2P-A SOP14-P-225-1 MS-012AB
Contextual Info: 14P2P-A Plastic 14pin 225mil SOP EIAJ Package Code SOP14-P-225-1.27 JEDEC Code MS-012AB Weight g 0.12 Lead Material Cu Alloy e 8 1 7 E Recommended Mount Pad F A Symbol D A2 A1 b y L e L1 HE e1 I2 14 b2 c Detail F A A1 A2 b c D E e HE L L1 y b2 e1 I2 Dimension in Millimeters
|
Original
|
14p2p-a14pin225milop14-p-225-1+3ms-012abms-012-absop14-p-225-1
|
PDF
|
IN7407N
Abstract: IN7407
Contextual Info: TECHNICAL DATA IN7407 Hex Buffers/Drivers with OpenCollector High-Voltage Outputs LOGIC DIAGRAM ORDERING INFORMATION IN7407N Plastic IN7407D SOIC TA = -10° to 70° C for all packages PIN ASSIGNMENT FUNCTION TABLE PIN 14 =VCC PIN 7 = GND Inputs Output A Y
|
Original
|
in7407in7407nin7407d012ab |
PDF
|
in744
Abstract: 1N3064 1N916 IN7440
Contextual Info: TECHNICAL DATA IN7440 Dual 4-Input Positive-NAND Buffers LOGIC DIAGRAM ORDERING INFORMATION IN7440N Plastic IN7440D SOIC TA = -10° to 70° C for all packages PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND NC - No internal connection FUNCTION TABLE Inputs Output A
|
Original
|
in7440in7440nin7440d012ab+3in7441n30641n916
|
PDF
|
KK74LS04
Abstract: KK74LS04D KK74LS04N
Contextual Info: TECHNICAL DATA KK74LS04 Hex Inverters This device contains six independent inverts. It performs the Boolean function Y=A. ORDERING INFORMATION KK74LS04N Plastic KK74LS04D SOIC TA = -0° to 70° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE
|
Original
|
kk74ls04kk74ls04nkk74ls04d012ab |
PDF
|
1N3064
Abstract: 1N916 KK7440 KK7440D KK7440N
Contextual Info: TECHNICAL DATA KK7440 Dual 4-Input Positive-NAND Buffers LOGIC DIAGRAM ORDERING INFORMATION KK7440N Plastic KK7440D SOIC TA = -10° to 70° C for all packages PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND NC - No internal connection FUNCTION TABLE Inputs Output A
|
Original
|
kk7440kk7440nkk7440d012ab+21n30641n916
|
PDF
|
IN74LS04N
Abstract: IN74LS04
Contextual Info: TECHNICAL DATA IN74LS04 Hex Inverters This device contains six independent inverts. It performs the Boolean function Y=A. ORDERING INFORMATION IN74LS04N Plastic IN74LS04D SOIC TA = -0° to 70° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE
|
Original
|
in74ls04in74ls04nin74ls04d012ab |
PDF
|
KK7407
Abstract: KK7407D KK7407N
Contextual Info: TECHNICAL DATA KK7407 Hex Buffers/Drivers with OpenCollector High-Voltage Outputs LOGIC DIAGRAM ORDERING INFORMATION KK7407N Plastic KK7407D SOIC TA = -10° to 70° C for all packages PIN ASSIGNMENT FUNCTION TABLE PIN 14 =VCC PIN 7 = GND Inputs Output A Y
|
Original
|
kk7407kk7407nkk7407d012ab |
PDF
|
1N3064
Abstract: 1N916
Contextual Info: TECHNICAL DATA IN74180 9-Bit ODD/EVEN Parity Generators/Checkers ORDERING INFORMATION IN74180N Plastic IN74180D SOIC TA = -10° to 70° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND FUNCTION TABLE Inputs Σ of H’s at EVEN A Thru H
|
Original
|
in74180in74180nin74180d012ab+21n30641n916
|
PDF
|
1N3064
Abstract: 1N916 IN74LS86D IN74LS86N
Contextual Info: TECHNICAL DATA IN74LS86 Quad 2-Input Exclusive OR Gate This device contains four independent 2-input Exclusive-OR gates. It performs the Boolean functions Y=A ⊕ B=AB+AB in positive logic. ORDERING INFORMATION IN74LS86N Plastic IN74LS86D SOIC TA = 0° to 70° C for all packages
|
Original
|
in74ls86in74ls86nin74ls86d012ab+21n30641n916
|
PDF
|
1N3064
Abstract: 1N916 KK74LS86 KK74LS86D KK74LS86N
Contextual Info: TECHNICAL DATA KK74LS86 Quad 2-Input Exclusive OR Gate This device contains four independent 2-input Exclusive-OR gates. It performs the Boolean functions Y=A ⊕ B=AB+AB in positive logic. ORDERING INFORMATION KK74LS86N Plastic KK74LS86D SOIC TA = 0° to 70° C for all packages
|
Original
|
kk74ls86kk74ls86nkk74ls86d012ab+21n30641n916
|
PDF
|
1N3064
Abstract: 1N916 KK74180 KK74180D KK74180N
Contextual Info: TECHNICAL DATA KK74180 9-Bit ODD/EVEN Parity Generators/Checkers ORDERING INFORMATION KK74180N Plastic KK74180D SOIC TA = -10° to 70° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND FUNCTION TABLE Inputs Σ of H’s at EVEN A Thru H
|
Original
|
kk74180kk74180nkk74180d012ab+21n30641n916
|
PDF
|
IN747
Abstract: 1N3064 1N916
Contextual Info: TECHNICAL DATA IN7472 AND-Gated J-K Master-Slave FlipFlops with Reset and Clear LOGIC DIAGRAM ORDERING INFORMATION IN7472N Plastic IN7472D SOIC TA = -10° to 70° C for all packages PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND NC - No internal connection FUNCTION TABLE
|
Original
|
in7472in7472nin7472d012ab+3in7471n30641n916
|
PDF
|
KK4002B
Abstract: KK4002BD KK4002BN
Contextual Info: TECHNICAL DATA KK4002B Dual 4-Input NOR Gate High-Voltage Silicon-Gate CMOS The KK4002B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature
|
Original
|
kk4002bkk4002bnkk4002bd012ab |
PDF
|
|
|
IW4025BD
Abstract: IW4025BN
Contextual Info: TECHNICAL DATA IW4025B Triple 3-Input NOR Gate High-Voltage Silicon-Gate CMOS The IW4025B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature
|
Original
|
iw4025biw4025bniw4025bd012ab |
PDF
|
KK4071B
Abstract: KK4071BD KK4071BN
Contextual Info: TECHNICAL DATA KK4071B Quad 2-Input OR Gate High-Voltage Silicon-Gate CMOS The KK4071B OR gates provide the system designer wich direct emplementation of the positive-logic OR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature
|
Original
|
kk4071bkk4071bnkk4071bd012ab |
PDF
|
1N3064
Abstract: 1N916 KK7472 KK7472D KK7472N
Contextual Info: TECHNICAL DATA KK7472 AND-Gated J-K Master-Slave FlipFlops with Reset and Clear LOGIC DIAGRAM ORDERING INFORMATION KK7472N Plastic KK7472D SOIC TA = -10° to 70° C for all packages PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND NC - No internal connection FUNCTION TABLE
|
Original
|
kk7472kk7472nkk7472d012ab+21n30641n916
|
PDF
|
KK4081B
Abstract: KK4081BD KK4081BN
Contextual Info: TECHNICAL DATA KK4081B Quad 2-Input AND Gate High-Voltage Silicon-Gate CMOS The KK4081B AND gates provide the system designer with direct emplementation of the AND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature
|
Original
|
kk4081bkk4081bnkk4081bd012ab |
PDF
|
KK4011B
Abstract: KK4011BD KK4011BN
Contextual Info: TECHNICAL DATA KK4011B Quad 2-Input NAND Gate High-Voltage Silicon-Gate CMOS The KK4011B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature
|
Original
|
kk4011bkk4011bnkk4011bd012ab |
PDF
|
IW4081BD
Abstract: IW4081BN
Contextual Info: TECHNICAL DATA IW4081B Quad 2-Input AND Gate High-Voltage Silicon-Gate CMOS The IW4081B AND gates provide the system designer with direct emplementation of the AND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 A at 18 V over full package-temperature
|
Original
|
iw4081biw4081bniw4081bd012ab |
PDF
|
KK4025B
Abstract: KK4025BD KK4025BN
Contextual Info: TECHNICAL DATA KK4025B Triple 3-Input NOR Gate High-Voltage Silicon-Gate CMOS The KK4025B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature
|
Original
|
kk4025bkk4025bnkk4025bd012ab |
PDF
|
IW4023BN
Abstract: IW4023BD
Contextual Info: TECHNICAL DATA IW4023B Triple 3-Input NAND Gate High-Voltage Silicon-Gate CMOS The IW4023B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 A at 18 V over full package-temperature
|
Original
|
iw4023biw4023bniw4023bd012ab |
PDF
|
KK4001B
Abstract: KK4001BD KK4001BN
Contextual Info: TECHNICAL DATA KK4001B Quad 2-Input NOR Gate High-Voltage Silicon-Gate CMOS The KK4001B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature
|
Original
|
kk4001bkk4001bnkk4001bd012ab |
PDF
|
IW4071B
Abstract: IW4071BD IW4071BN
Contextual Info: TECHNICAL DATA IW4071B Quad 2-Input OR Gate High-Voltage Silicon-Gate CMOS The IW4071B OR gates provide the system designer wich direct emplementation of the positive-logic OR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 A at 18 V over full package-temperature
|
Original
|
iw4071biw4071bniw4071bd012ab |
PDF
|
