MR 4030 Search Results

TLS2271

Abstract: 32H6742 schematic diagram of seagate hard disk pcb tls2270 TLS2247 TLS2251 TLS2245 1575R SP4107A 32H6910
Contextual Info: TABLE OF CONTENTS How to use the Data CD-ROM Texas Instruments Storage Products Overview Alpha/Numeric Index 2000 Short Form Catalog Discontinued Parts List DSP and ASIC Quality and Technology HDD Read/Write Amplifiers MR Head Read/Write Thin-Film Head Read/Write

Str mr 4010

Abstract: MR 4010 str 3050 fitting PG lapp plug atex 5200 str 4090
Contextual Info: Cable Glands - brass gland components Brass gland components. TYPE ME Useful for enlarging a tapped hole or for fitting to a panel to accept a gland. Both threads are PG in nickel-plated brass. TYPE ME TYPE MR Used for the reverse of the ME, i.e. to reduce the size of a

3S035T-1

Abstract: tungsram 3S035T-1 12QR205 5Q105 4S040T-1 grg 250 5S045T SRS 4451 tungsram RS 329g
Contextual Info: TUNGSRAM 1> r SENDEROHREN SENDETRIODEN SENDETETRODEN SENDEPENTODEN •• GLEICHRICHTERRÖHREN HOCHSPANNUNGS­ GLEICHRICHTERRÖHREN THYRATRONS SENDITRONS ' • . -• MIKROWEILENRÖHREN REFLEXKLYSTRONS WANDERFELDRÖHREN T Y P E N V E R Z E IC H N IS TYP SEITE

mr 4020 pin assignment

Abstract: MC100E150
Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

MC100E150

Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

MC100E150

Abstract: mr 4020 MC100E150FN MC100E150FNR2 MC10E150 MC10E150FN MC10E150FNR2
Contextual Info: MC10E150, MC100E150 5VĄECL 6ĆBit D Latch The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

MC100E150

Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

mr 4020

Abstract: mr 4030 MC100E150 MC10E150 MC10E150FN ul 1950
Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

MC100E150

Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

MC100E150

Abstract: MC10E150 MC10E150FN
Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

MC100E150

Abstract: MC100E150FN MC100E150FNR2 MC10E150 MC10E150FN MC10E150FNR2 mr 4030
Contextual Info: MC10E150, MC100E150 5VĄECL 6ĆBit D Latch The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

MC100E150

Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

4017BP

Abstract: 4013BP 4069BP 4016BP 4066bp hef 4011bp IC NAND 4040BP 4000BP 40106BP 4030BP
Contextual Info: Signetics Integrated Circuits - Loemos HEF 4000 Series LOCIMOS Locally Oxidised CMOS LOCM OS g e n e r a l d e s c r ip t io n LOCMOS is com ple tely pin, fu n c tio n and ty p e num ber com patible w ith th e 4 0 0 0 and 14000 fam ilies. Compared w ith o rd in a ry CMOS, LOCMOS c irc u it

mr 4020

Abstract: MC100E175
Contextual Info: MC10E175, MC100E175 5V ECL 9-Bit Latch With Parity The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs ODDPAR is HIGH if an odd number of the inputs are HIGH . The E175 can also be used to generate byte parity by using D8 as the

transistor phl 815

Contextual Info: MC10E141, MC100E141 5V ECL 8-Bit Shift Register The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0 − D7 accept parallel input data, while

Contextual Info: MC10E155, MC100E155 5V ECL 6−Bit 2:1 Mux−Latch The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic

Contextual Info: MC10E143, MC100E143 5V ECL 9-Bit Hold Register The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 − D8 accepting parallel input data. The SEL Select input pin is used to switch between the two modes

Contextual Info: O T National Semiconductor À jÉ 54F/74F403 First-In First-Out FIFO Buffer Memory General Description Features The ’F403 is an expandable (all-through type high-speed First-In First-Out (FIFO) Buffer Memory optimized for high­ speed disk or tape controllers and communication buffer

Contextual Info: MC10E154, MC100E154 5V ECL 5-Bit 2:1 Mux-Latch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on

Contextual Info: MC10E167, MC100E167 5V ECL 6-Bit 2:1 MUX-Register The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 or both . A HIGH on

MC100E175

Abstract: E175 MC100E175FN MC100E175FNR2 MC10E175 MC10E175FN MC10E175FNR2 E175 transistor
Contextual Info: MC10E175, MC100E175 5VĄECL 9ĆBit Latch With Parity The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs ODDPAR is HIGH if an odd number of the inputs are HIGH . The E175 can also be used to generate byte parity by using D8 as the

MC100E151

Abstract: MC100E151FN MC100E151FNR2 MC10E151 MC10E151FN MC10E151FNR2
Contextual Info: MC10E151, MC100E151 5V ECL 6-Bit D Register The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous

mr 4020

Abstract: MC100E151 MC100E151FN MC100E151FNR2 MC10E151 MC10E151FN MC10E151FNR2
Contextual Info: MC10E151, MC100E151 5VĄECL 6ĆBit D Register The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous

socket 775 pinout

Abstract: mr 4030
Contextual Info: MC10E156, MC100E156 5V ECL 3-Bit 4:1 Mux-Latch The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic