MODELER Search Results

Contextual Info: Chapter 15 - Back Annotation pASIC 2 Chapter 15: Back Annotation (pASIC 2) The Delay Modeler tool calculates the specific timing delays for the placed and routed pASIC device. The Back Annotation tool creates output files for logic simulation and fixing logic placement in QuickWorks. The Back Annotation tool puts

Contextual Info: Chapter 22 - Back Annotation pASIC 1 Chapter 22: Back Annotation (pASIC 1) The Delay Modeler tool is used to calculate the specific timing delays in the QuickLogic pASIC device. The Back Annotation tool sends these timing numbers to a simulator for back-annotated simulation, and creates .SCP and .ATR back annotated

vital 3.0

Contextual Info: Chapter 8 - Back Annotation Chapter 8: Back Annotation The Delay Modeler tool calculates the specific timing delays for the placed and routed pASIC device. The Back Annotation tool creates output files for logic simulation and fixing logic placement in QuickWorks. The Back Annotation tool puts

nurbs

Contextual Info: Amapi 3D* v5.1 Template Graphics Software, Inc. Amapi 3D* is a powerful and versatile modeler. It simplifies the creation and editing of complex geometric shapes by offering a large selection of advanced tools. Due to its customizable interface, Amapi 3D meets the needs of professional designers, while

k-means

Abstract: Intelligence Access system
Contextual Info: IBM Software Business Analytics IBM SPSS Modeler Professional IBM SPSS Modeler Professional Make better decisions through predictive intelligence Highlights Create more effective strategies by evaluating trends and likely outcomes. • Easily access, prepare and model

AXE 10 pstn

Abstract: Ericsson HLR Signaling transfer point ericsson STP ericsson AXE switch ERICSSON Ericsson AXE 10 The SDH interface in AXE ericsson axe PSTN concepts pstn simulator
Contextual Info: RU QHWZRUN GHVLJQ DQG VLPXODWLRQ 3URGXFW 'HVFULSWLRQ TEMS Modeler Product Description The contents of this document are subject to revision without notice due to continued progress in methodology, design and manufacturing. Ericsson assumes no legal responsibility for any error or damage resulting from the

churn

Abstract: k-means social networks
Contextual Info: IBM Software Business Analytics IBM SPSS Modeler Premium IBM SPSS Modeler Premium Improve model accuracy with structured and unstructured data, entity analytics and social network analysis Highlights Solve business problems faster with analytical techniques that deliver

n20s

Abstract: A144 BG256 IEEE1164 Military Plastic pASIC 3 Family 256
Contextual Info: 3T PRELIMINARY CYPRESS Ultra38007 UltraLogic Very High Speed 7K Gate CMOS FPGA Features — Minimum Iol and Ioh 24 mA Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay

CY7C381P

Abstract: CY7C381P-0JC CY7C381P-XJC CY7C381P-XJI CY7C382P CY7C383A CY7C385P 100-Pin CPGA Package Pin-Out Diagram
Contextual Info: CY7C381P CY7C382P CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns • Unparalleled FPGA performance for counters, data path, state machines,

Contextual Info: IBM Software Business Analytics IBM Analytical Decision Management IBM Analytical Decision Management Deliver better outcomes in real time, every time Highlights Organizations of all types can maximize outcomes with IBM Analytical Decision Management, which enables you to:

CY7C3381A

Abstract: CY7C3381A-0JC CY7C3381A-0JI CY7C3381A-XJC CY7C3382A CY7C3384A CY7C3385A 00252-B
Contextual Info: CY7C3381A CY7C3382A CYPRESS Features • Very high speed — Loadable counter frequencies greater than SO MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithmetic, and random logic

frws 5-4

Abstract: CY7C381-0JI C3816 G68 Package vhdl code for lte channel coding CY7C381 CY7C382 7c381 C381-9 C3812
Contextual Info: ¡iiö i id in tJ . iv iu iiu c iy , M u y u t ji i / , Revision: Wednesday, March 16,1994 ¥ CY7C381 CY7C382 cypress Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

C3202

Abstract: C32025 TMS320C25 test bench for 16 bit shifter C32025TX
Contextual Info: Control Unit o 16-bit instruction decoding o Repeat instructions for effi- C32025 Digital Signal Processor Core cient use of program space and enhanced execution Central Arithmetic-Logic Unit o 16-bit parallel shifter; 32-bit arithmetic and logical operations

intel 8051 Arithmetic and Logic Unit -ALU

Abstract: Memory Management 8051 8051 address decoder verilog code for ALU implementation 80C31 80C51 ASM51 SAB80C537 verilog code for 32 BIT ALU implementation verilog code for 8051
Contextual Info:  Control Unit − Eight-bit instruction decoder for MCS 51 instruction set R8051XC-EP 8051-Compatible Microcontroller Megafunction An economical, entry-point, fixed-configuration megafunction that implements an 8051-like 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as the 80C31, but executes operations an average of eight times faster.

8254 vhdl code

Abstract: 8259 Programmable Peripheral Interface intel 80386 block diagram intel 82380 8254 vhdl 82380 verilog code for 8254 timer 8259 interrupt controller vhdl code intel 8259 8259 programmable interval timer
Contextual Info:  Eight independently programm- able channels of 32-Bit DMA  Twenty source, individually pro- C82380 32-Bit DMA Controller with Integrated Support Peripherals Core grammable Interrupt channels o Fifteen external interrupts o 5 internal interrupts o Intel 8259 superset

c80186

Abstract: 80186EC 8259A intel FPGA 80C186EC 16X16 80C186EC C80187
Contextual Info: Control Unit: − 9-level deep and 1-byte wide instruction queue C80186EC 80186EC-Compliant Chip Replacement 16-bit Microcontroller Megafuction − Independent instruction ex- ecution stages allow instructions to overlap Arithmetic Logic Unit: − 16-bit arithmetic and logical

DOWN COUNTER using 8051

Abstract: R8051XC2 verilog code for 32 BIT ALU multiplication verilog code R8051XC2 80C51 frequency counter using 8051 alarm clock 8051 microcontroller uart verilog MODEL r8051xc2-b R8051XC2-AF
Contextual Info: Fully compatible with the MCS 51 instruction set R8051XC2 High-Performance, Configurable, 8-bit Microcontroller Core The R8051XC2 configurable processor core implements a range of fast, 8-bit, microcontrollers that execute the MCS®51 instruction set. The IP core runs with a single clock per machine cycle, and requires an average of 2.12

C3202

Abstract: C32025 TMS320C25 tsmc 0.18
Contextual Info: Control Unit o 16-bit instruction decoding o Repeat instructions for effi- C32025 Digital Signal Processor Core cient use of program space and enhanced execution Central Arithmetic-Logic Unit o 16-bit parallel shifter; 32-bit arithmetic and logical operations

tsmc 0.18

Abstract: C32025TX C32025 TMS320C25 ram tsmc 0.18
Contextual Info: Control Unit o Single-clock per machine cycle operation o 16-bit instruction decoding C32025TX o Repeat instructions for effi- Digital Signal Processor Core cient use of program space o 8-level Hardware Stack Central Arithmetic-Logic Unit o 16-bit sign-extended parallel

CZ80CPU

Abstract: Z84C00
Contextual Info: CZ80CPU 8-Bit Microprocessor Core The CZ80CPU implements a fast, fully-functional, single-chip, 8-bit microprocessor with the same instruction set as the Z80. The core has a 16-bit address bus capable of directly accessing 64kB of memory space. It has 252 root instructions with the reserved 4 bytes as prefixes, and accesses

SPARTAN-3 XC3S400

Abstract: CZ80CPU Z84C00
Contextual Info: CZ80CPU 8-Bit Microprocessor Core The CZ80CPU implements a fast, fully-functional, single-chip, 8-bit microprocessor with the same instruction set as the Z80. The core has a 16-bit address bus capable of directly accessing 64kB of memory space. It has 252 root instructions with the reserved 4 bytes as prefixes, and accesses

16X24B

Abstract: CF160 PF100 PF144 PL84 CPGA Package Diagram
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

IN314

Abstract: 96 pin euro connectors euro 96 DIN connector In114 VME COnnector IN313 IN211 euro 96 connector parallel port 25 pin connector CTL14
Contextual Info: HSP-EVAL USER’S MANUAL May 1999 File Number 3366.2 DSP Evaluation Platform Features The HSP-EVAL is the mother board for a set of daughter boards based on the HSPxxxxx family of Digital Signal Processing products. Each product specific daughter board is mated with the HSP-EVAL to provide a mechanism for

ad654 spice

Abstract: DARLINGTON TRANSISTOR ARRAY AD75019
Contextual Info: ANALOG DEVICES INC 51E D • OfllbflQQ 0 0 3 7 3 T M b42 ■ ANA - H7.-e>\ i r ■ MIXED SIGNAL M U M ' >Jlil\Ul' J.;! r l □ Q ANALOG DEVICES * ANALOG DEVICES INC 51E D ■ OfllbBOD 0 0 3 7 3 ^ 5 Table of Contents 1 Summary 2 ASIC Processes 5 LC2MOS Cell Library