MO-153 PACKAGES Search Results

JEDEC MO-153

Abstract: MO-153-BD-1 MO-153BD-1
Contextual Info: Plastic Packages for Integrated Circuits Thin Shrink Small Outline Plastic Packages TSSOP M38.173 N INDEX AREA E 0.25(0.010) M E1 2 INCHES GAUGE PLANE -B1 38 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-153-BD-1 ISSUE F) B M SYMBOL

Contextual Info: 1C 5 1 /5 3 SERIES S0P/QFP/QFN ICC /QF1(PLCC)/TCP FEATURES • • S ockets tor SOP, QFP and other surface-m ount 1C packages. Custom designs also available for m ulti-lead, fine-pitch and other special packages. SPECIFICATIONS PERFORMANCE Contact our Sales Department for detail. Specifications differ by the contact

Avantek amplifier

Abstract: transistor tt 2206 TT 2206 Avantek, Inc. GPD 35C05 LMM 2057 GPD-201 Avantek rf amplifier GPD-1001 GPD-405 GPD-331
Contextual Info: AVANTEK INC EOE O a v a n tek D • i m i l t t 0QQ7343 Selection G uide 4 GPD Series PRODUCT DESCRIPTION The GPD and G PM amplifiers, available in TO-12 4-pin and TO-39 (3-pin) packages, are designed for applications which require the highest performance-to-cost ratio or where size is

Contextual Info: THICK FILM CONFORMAL SIPs, HIGH PROFILE 4 THROUGH 14 PIN • High profile offers increased power handling ■ Wide assortment of pin packages enhances design flexibility ■ Ammo-pak packaging available n Recomrr ended for rosin flux and solvent clean or no clean

eel -16

Abstract: RS481
Contextual Info: TAPE AND REEL SPECIFICATIONS SUBMINIATURE PACKAGES OPTOELECTRONICS Ordering In fo rm atio n To order Q E B or Q SB subminiature products on tape and reel include the appropriate standard product part num ber and suffix code to specify the lead form and packaging method.

R1C11

Abstract: r6c1
Contextual Info: Configuration selection generates starting addresses at either zero or 3FFFF, to be compatible with different microprocessor addressing conventions. The Master Serial Mode generates CCLK and receives the configuration data in serial form from configuration data in serial form from a

Contextual Info: Product Color Information Plastic Enclosures: Beige Blue Black Grey Painted Diecast Aluminum Enclosures: Black Watertight - 1590Z Series Grey RAL 7001 General Purpose Metal Enclosures: Black Contempra Grey (RAL 7032) Blue ASA 61 Grey NOTE: This color chart page is included for reference only. It was created with printers ink and gives

TsE 151

Abstract: transistor irfp IRFP152 IRFP150 IRFP 150fi IRFP P CHANNEL IRFP150FI IRFP151 IRFP transistors
Contextual Info: _ 30E D m 7CJ2C1537 GQS^ÖSS 2 • ^ T 7'3 0 |-|3 7 SCS-THOMSON Mmi[LEg¥[E«P g§ L 1 _ S" TH0MS0N TYPE IRFP150 IRFP150FI IRFP151 IRFP151FI IRFP152 IRFP152FI IRFP153 IRFP153FI Vpss 100 V 100 V 60 V 60 V 100 V 100 V 60 V 60 V IRFP 150/FI-151/FI IRFP 152/FI-153/FI

Contextual Info: 1. 5 P o w e r P C 6 0 3 e M i c r o p r o c e s s o r Pi n A s s i g n m e n t s The following sections contain the pinout diagrams for the 603e. Note that the 603e is offered in both ceramic quad flat pack CQFP and ceramic ball grid array (CBGA) packages.

Contextual Info: THICK FILM CONFORMAL SIPs ULTRALOW PROFILE, 4 THROUGH 12 PIN • Low profile is compatible with DIPs ■ Wide assortment of pin packages enhances design flexibility ■ Recommended for rosin flux and solvent clean or no clean flux processes Model 4600U Resistor Networks

xc4413

Abstract: P23S Xilinx XC4013 XC4410 P181 V8 XC4406 XC4405 XC4403 xc442 XC4400
Contextual Info: £ XILINX* XC4400 Hardwire Array Family Preliminary Product Specification Features Description • Mask-programmed versions of Programmable Logic Cell Arrays FPGA The XC4400 Series Hardwire Arrays are advanced maskprogrammed versions of the XC4000 programmable de­

XC5402

Abstract: XC5406 XC5410
Contextual Info: f l XILINX XC5400 Hardwire Array Family Preliminary Product Specification Features Description • Mask Programmed version of the XC5200 Field Programmable Gate Array FPGA - Specifically designed for easy XC5200 conversion - Significant cost reduction for high volume

Contextual Info: THICK FILM CONFORMAL SIPs, LOW PROFILE 4 THROUGH 16 PIN • Low profile is compatible with DIPs ■ Wide assortment of pin packages enhances design flexibility ■ Ammo-pak packaging available ■ Recommended for rosin flux and solvent clean or no clean flux processes

5200 FPGA

Abstract: PC8421
Contextual Info: SIXILINX* XC5400 Hardwire Array Family Preliminary Product Specification Features Description • Mask Programmed version of the XC 5200 Reid Programmable G ate Array FPGA - Specifically designed for easy XC 5200 conversion - Significant cost reduction for high volume

xc4413

Abstract: ATIC 164 D2 XC4013 PG223 xc4405 cn/A/U 237 BG
Contextual Info: f i XILINX XC4400 Hardwire Array Family Preliminary Product Specification Features Description • Mask-programmed versions of Programmable Logic Cell Arrays FPGA The XC4400 Series H ardw ire Arrays are advanced maskprogrammed versions of the XC4000 programmable de­

Contextual Info: KMM37 2 V 4 0 0 B K D R A M Mo d u l e ELECTRO NICS KMM372V400BK/BS / KMM372V41OBK/BS Fast Page Mode 4Mx72 DRAM DIMM with ECC, 4K & 2K Refresh, 3.3V GENERAL DESCRIPTION FEATURES • Part Identification The Samsung KMM372V40 1 0B is a 4M bit x 72 Dynamic RAM high density memory module. The

Contextual Info: JIXILINX XC5200 Field Programmable Gate Arrays June 1, 1996 Version 4.0 Preliminary Product Specification Features • Fully supported by XACTsfep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed

gc 7137 ad

Abstract: transistor c5200 c5200 transistor TTC 5200 C5200 LC1 D18 P7 HC 148 TRANSISTOR ATIC 164 D2 44 pin
Contextual Info: £ XILINX XC5200 Series Field Programmable Gate Arrays Novem ber 5, 1998 Version 5.2 Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogram m able architecture - 0.5|j.m three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)

XC3330A

Abstract: P2M3 XC3390A
Contextual Info: ' K x il in x XC3300A/L Hardwire Array Family * Preliminary Product Specification Features Description • Mask-programmed versions of Xiiinx Programmable Logic Cell Arrays XC3000, XC3000A, XC3000L, XC3100, XC3100A - Cost reduction for high volume applications

ic 4082 16 pins

Abstract: ic 4082 ic 4082 and pin configuration
Contextual Info: IP X fd t Integrated Ete1i'ice Technology, Inc. Inf7MBV4150 128K x 64/256K x 72 SYNC HR ON OUS PIPELINED BU RST SRAM 256K x 72 BU RST Z B T SRAM MODULE FAMILY IDT7MBV4151 IDT7MBV4152 FEATURES: DESCRIPTION: • Pin compatible module family for pipelined burst SRAM and

XC3342

Contextual Info: f i XI LI N X XC3300A/L Hardwire Array Family Preliminary Product Specification Features Description • The Xilinx XC3300A/L family of H ardwire Arrays are mask programmed versions of the Xilinx XC3000A/L/XC3100A FPGAs. In high-volume applications where the design is

CMP01CP

Abstract: CMP01EZ CMP-01 cmp01ep cmp01cj CMP01CZ CMP01EJ CMP01Z CMP01J CMP-01CJ
Contextual Info: Fast Precision Comparator CMP-01 AN ALO G DEVICES GENERAL DESCRIPTION fea tu r es • • • • • a • a • • • • Fast Response Time . 180nsMax High Input Slaw R

XCS200 FPGA

Contextual Info: HXILINX XC5200 Series Field Programmable Gate Arrays December 10, 1997 Version 5.0 Product Specification Features • • Low-cost, process-optimized, register/latch rich, SRAM based reprogrammable architecture - 0.5pm three-layer metal CMOS process technology

ATIC 164 D2 44 pin

Abstract: ATIC 164 D2 48 pin ATIC 164 D3
Contextual Info: H X IL IN X XC5200 Field Programmable Gate Arrays June 1, 1996 Version 4.0 Prelim inary Product Specification Features • • High-density family of Field-Program m able Gate Arrays (FPGAs) • Design- and process-optimized for low cost - 0.6-nm three-layer metal (TLM) process