MK5029 Search Results

DIP48

Abstract: DIP-48 MK5025 MK5027N MK5027Q MK50H25N MK50H25Q MK50H27 MK50H27Q MK50H28N
Contextual Info: TELECOM AND DATA COMMUNICATIONS DATACOM PACKET SWITCHING/CCS#7 Type MK5025 MK50H25Q MK50H25N MK5027Q MK5027N MK50H27 MK50H27Q MK50H28Q MK50H28N MK5029 Description Package X 25 LAPB/ISDN LAPD/HDLC CMOS Hi-Speed Link Level Controller with DMA X 25 Link Level Controller

mk5021

Abstract: DIP-48 DIP48
Contextual Info: TELECOM AND DATA COMMUNICATIONS DATACOM PACKET SWITCHING/CCS#7 Type MK5025 MK50H25Q MK50H25N MK5027Q MK5027N MK50H28Q MK50H28N MK5029 Description Package X 25 LAPB/ISDN LAPD/HDLC CMOS Hi-Speed Link Level Controller with DMA X 25 Link Level Controller X 25 Link Level Controller

GA27-3093-2

Abstract: DAL00
Contextual Info: rz 7 S C S -T H O M S O N TECHNICAL MANUAL MK5029 SDLC LINK LEVEL CONTROLLER TABLE OF CONTENTS SECTION PAGE SECTION 1 INTRODUCTION Introduction 3 SECTION 2 FEATURES Feature 3 SECTION 3 OPERATIONAL DESCRIPTION 3.1 Functional B lo c k s .

80386SX

Abstract: DIP48 MK5025 MK5027 MK50H25 Z8000 dali Receiver 80286 instruction
Contextual Info: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst

Contextual Info: SGS-TtiOMSON MK50H28 • U K ê T IM M Ê i MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES ■ Based on ITU Q.933 Annex A and T1.617 An­ nex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs .

Contextual Info: MK50H25 HIGH SPEED X.25 LINK LEVEL CONTROLLER PRODUCT PREVIEW • Fully com patible with both 8 or 16 bit systems. ■ System clock rate up to 33 MHz. ■ Data rate up to 20 Mbps continuous or up to 50 Mbps bursted ■ Separate 64-byte Transm it and Receive FIFO.

mk5021

Abstract: N393 BCNT DIP48 MK5027 MK50H28 PLCC52 Z8000 A 1905 LMI
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

AN489

Abstract: mk5021 an-490 AN-489 mk5021 technical manual
Contextual Info: ALPHANUMERICAL INDEX ISDN Type Number Function Page GS1T70-D540 ISDN DC-DC Converter 275 ST5080 Piafe Programmable ISDN Audio Front End 245 ST5410 2B1QU Interface Device 27 ST5410 User Manual 81 ST5420 Sid-^W : S/T Interface Device with Microwire/DSI 153 ST5421

mk5021

Abstract: TSW 8088 SRS 4451 DE-A1D
Contextual Info: ^ 7 ^ 7 # « S G S -T H O M S O N IM » iL [Ì g » S l(g § TECHNICAL MANUAL MK5021 SERIAL COMMUNICATIONS CONTROLLER TABLE OF CONTENTS SECTION PAGE SECTION 1 INTRODUCTION Introduction 3 SECTION 2 FEATURES Features 3 SECTION 3 OPERATIONAL DESCRIPTION 3.1 Functional B lo c k s .

STR d 4412 PINS DETAILS

Abstract: dali n39l
Contextual Info: SGS-THOMSON iH lM M O e s M K 5 0 H 2 8 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES • Based on ITU Q.933 Annex A and T1.617 An­ nex D Standards for Frame Relay Service and Additional Pocedures tor Permanent Virtual Circuits PVCs . ■ Optional Transparent Mode (no LMI Protocol

DIP48

Abstract: MK5021 MK5027 MK50H28 PLCC52 Z8000
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER ADVANCE DATA SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent (or no LMI/LIV Protocol

uav design specification

Abstract: water filling station circuit diagram DALI CONTROL logical block diagram of 80286 uav electronic design water level controller using timer 555 8086 microprocessor pin description control data bus for 80286 uav design z80 cio
Contextual Info: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst

mk7990

Abstract: MK5021Q10 marking r01f mk5027q10 CSR 41b datasheet SMD R01f 48-PIN MK5025 PLCC52 mk5021
Contextual Info: • 7^21237 D OMSa ^a 3ñT M S G T H SGS-THOMSON _ MK5025 CCITT X.25 LINK LEVEL CONTROLLER P R E L IM IN A R Y D A T A . CMOS ■ FULLY COMPATIBLE WITH BOTH 8-BIT OR 16-BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATE RATE UP TO 7Mbps, WITH A 64-BYTE

Contextual Info: /= 7 ^ 7 # . S G S -T H O M S O N MK50H28 [fö i] D ^ © [i[L [l© T O R ! ]D © i MULTI LOGICAL LINK FRAME RELAY CONTROLLER ADVANCE DATA SECTION 1 - FEATURES • Based on ITU Q.933 Annex A and T1.617 An­ nex D Standards for Frame Relay Service and

Contextual Info: SGS-THOMSON MK50H25 HIGH SPEED X.25 LINK LEVEL CONTROLLER PRODUCT PREVIEW Fully compatible with both 8 or 16 bit systems. System clock rate up to 33 MHz. Data rate up to 20 Mbps continuous or up to 50 Mbps bursted Separate 64-byte Transmit and Receive FIFO.

Contextual Info: SGS-THOMSON ü * fô H H d g ïï[iM D ( g ! M K 5 0 2 5 CCITT X.25 LINK LEVEL CONTROLLER P R E L IM IN A R Y D A T A • CMOS ■ FULLY COM PATIBLE WITH BOTH 8-BIT OR 16-BIT SYSTEMS . SYSTEM CLOCK RATE TO 10MHz ■ DATE RATE UP TO 7Mbps, WITH A 64-BYTE

Contextual Info: r= 7 * • 1 /, S G S 'T H O M S O N MK50H25 M is œ U E ig T M O e i HIGHSPEED LINK LEVEL CONTROLLER AD VA N C E DATA SECTION 1 - FEATURES • System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). ■ Data rate up to 20 Mbps continuous

Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER ADVANCE DATA SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent (or no LMI/LIV Protocol

80386SX

Abstract: DIP48 MK5025 MK5027 MK50H25 Z8000 dali power supply circuit diagram dali master many
Contextual Info: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst

Contextual Info: 7 7 SGS-THOMSON k7 MK50H28 /. MULTI LOGICAL LINK FRAME RELAY CONTROLLER ADVANCE DATA SECTION 1 - FEATURES • Based on ITU Q.933 Annex A and T1.617 An­ nex D Standards for Frame Relay Service and Additional Pocedures tor Permanent Virtual Circuits PVCs .

dali

Abstract: DALI CONTROL DAL12
Contextual Info: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst

DALI rc BASIC SO

Contextual Info: SGS-THOMSON MK50H25 HIGHSPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES • System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). ■ Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted

DIP48

Contextual Info: gg 7 cüBc133? QQ4S433 flTb • S6TH /^ 7 SGS-THOMSON ^ 7 A MK50H25 K ffllM IllL I M W ö ® HIGH SPEED X.25 LINK LEVEL CONTROLLER PRODUCT PREVIEW ■ Fully compatible with both 8 or 16 bit systems. ■ System clock rate up to 33 MHz. ■ Data rate up to 20 Mbps continuous or up to