DAL15 Search Results

FOOTPRINT PCB

Abstract: DEL09PDTK1YS DAL15SDTK2YS
Contextual Info: D-Sub D-Sub Right Angle - 10.2mm Footprint PCB Connectors Positions Dimensions A B C Boardlocks & Jackscrews D Plugs Sockets Boardlocks & 4-40 UNC Inserts Plugs Sockets 9 16.92 24.99 30.81 16.33 DEL09PDTK1YS DEL09SDTK2YS DEL09PDTK1NS DEL09SDTK2NS 15 25.25 33.32 39.14 24.66 DAL15PDTK1YS DAL15SDTK2YS DAL15PDTK1NS DAL15SDTK2NS

dale r01f

Abstract: MK68H MK68590 r01f dale MK68200 Z8000 MOSTEK ROM r01f mostek MK5025 IN914
Contextual Info: MK5025 P R E L IM IN A R Y C O M M U N IC A T IO N S PR O O U C TS FEATURES DAL04 £ £ 3 £ 4 £ S £ Z Data rate up to 7 MBPS with 64 bytes FIFOs in each direction. DAL03 6 C DA102 7 DAL01 1 H Z Complete Date Link Layer Implementation. DALDQ £ £ 11 £

A1023

Contextual Info: Components for GPS Receivers Dielectric Microwave Antenna Elements Frequency Control Products Standard Specifications Dimensions mm Part Number L H A B C D Nominal Centre -10dB Frequency Bandwidth Φ1 (MHz) (MHz) VSWR at CF (Max) (RL at CF dB) Polarization

80386SX

Abstract: DIP48 MK5025 MK5027 MK50H25 Z8000 dali Receiver 80286 instruction
Contextual Info: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst

Contextual Info: SGS-TtiOMSON MK50H28 • U K ê T IM M Ê i MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES ■ Based on ITU Q.933 Annex A and T1.617 An­ nex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs .

mk5021

Abstract: N393 BCNT DIP48 MK5027 MK50H28 PLCC52 Z8000 A 1905 LMI
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol

Contextual Info: A m 79C 900 In t e g r a te d L o c a l A re a C o m m u n ic a tio n s C ontroller ILACC™ Distinctive Characteristics. 1-51 General Description. 1-51

Contextual Info: PRELIMINARY Am79C900 Integrated Local Area Communications Controller ILACC™ Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Integrated Ethernet controller and Serial Interface Adapter. ■ 32-bit bus interface with programmable capability for easy interface to popular bus

N393

Abstract: DIP48 MK50H25 MK50H27 MK50H28 PLCC52 Z8000 DAL13
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol

JT-Q703

Abstract: MK50H27Q-33 bsnt1
Contextual Info: MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements

Q703

Abstract: DIP48 MK50H25 MK50H27 MK50H28 Z8000 JT-Q703 68000 thomson
Contextual Info: MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements

mk5021

Abstract: TSW 8088 SRS 4451 DE-A1D
Contextual Info: ^ 7 ^ 7 # « S G S -T H O M S O N IM » iL [Ì g » S l(g § TECHNICAL MANUAL MK5021 SERIAL COMMUNICATIONS CONTROLLER TABLE OF CONTENTS SECTION PAGE SECTION 1 INTRODUCTION Introduction 3 SECTION 2 FEATURES Features 3 SECTION 3 OPERATIONAL DESCRIPTION 3.1 Functional B lo c k s .

H4R15RA29C

Abstract: H4M09RA29C DCL-37-SCT-ZH
Contextual Info: D-SUB: .590" RT ANGLE threaded Insert DIM ENSIONS fo r k e d b o a rd lo c k s o n h a lf fla n g e 8 00 MOUNTING H O LE FLAN G E t 14 . 9 9 .590 Y FO O TP R IN T forkeo ¿-F0 ELECTRICAL BOARO LO C K CONTACT CURRENT RATING: 5 AMP DIELECTRIC WITHSTANDING:

DEL-09-PBT

Abstract: del09pbt 747844-3 747845-3 dal15sbt DEL-09-SBT
Contextual Info: D-SUB: .318" RT ANGLE threaded in sert 1 DIMENSIONS MOUNTING ( 4 - 4 0 ) THREADED RI VETED INSERT I SB nun Inc»» ELECTRICAL CONTACT CURRENT RATING: SAMP DIELECTRIC WITHSTANDING: 1000 VAC FOR 1 MINUTE P.C.B. Hole Pattern INSULATION RESISTANCE 1000 MOHMS @ 500 VDC

DIP48

Abstract: MK5021 MK5027 MK50H28 PLCC52 Z8000
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER ADVANCE DATA SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent (or no LMI/LIV Protocol

DIP48

Abstract: MK50H25 MK50H27 MK50H28 PLCC52 Z8000 BCNT
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol

traffic light controls using 8086

Abstract: traffic light 8086 ic laf 0001 Supply Control LAF 0001 10BASE Z8000 microprocessor closed loop control dali s1.2 am7990 laf 0001 power
Contextual Info: Am7990 Advanced Micro Devices Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS Compatible with Ethernet and IEEE 802.3 10BASE 5 Type A, and 10BASE 2 Type B, “Cheapernet” • Network and packet error reporting ■ Back-to-back packet reception with as little as

uav design specification

Abstract: water filling station circuit diagram DALI CONTROL logical block diagram of 80286 uav electronic design water level controller using timer 555 8086 microprocessor pin description control data bus for 80286 uav design z80 cio
Contextual Info: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst

mk7990

Abstract: MK5021Q10 marking r01f mk5027q10 CSR 41b datasheet SMD R01f 48-PIN MK5025 PLCC52 mk5021
Contextual Info: • 7^21237 D OMSa ^a 3ñT M S G T H SGS-THOMSON _ MK5025 CCITT X.25 LINK LEVEL CONTROLLER P R E L IM IN A R Y D A T A . CMOS ■ FULLY COMPATIBLE WITH BOTH 8-BIT OR 16-BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATE RATE UP TO 7Mbps, WITH A 64-BYTE

80486 microprocessor pin out diagram

Abstract: architecture of 80486 microprocessor DIP48 MK50H25 MK50H27 MK50H28 Z8000 JT-Q703
Contextual Info: S G S -T H O M S O N ^ D g W [llL i ¥ ^ (Q K 5 0 © S M K 5 0 H 2 7 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols.

SRS 4451

Contextual Info: / = T S G S -T H O M S O N MK50H25 HIGHSPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES • System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25- 16). ■ Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted

Contextual Info: H ZT ^7 M S G S -T H O M S O N M fg M ir a F M R Ä S M K50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES • Complete Level 2 Implementation of SS7. ■ Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols.

17BM1

Contextual Info: PRELIMINARY AMDZ1 Am79C90 CMOS Local Area Network Controller for Ethernet C-LANCE DISTINCTIVE CHARACTERISTICS • Compatible with Ethernet and IEEE 802.3 10BASE-5Type A, and 10BASE-2Type B, “C h e a p e rn e t1 0 B A S E -T ■ Easily interfaced with 80x86, 680x0, Am29000@,

AM22V10

Abstract: E5ES E5ES MODE PAL16L8 programming algorithm dali power supply circuit diagram CSRQ
Contextual Info: Am7990* Am7990* Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS Ethernet and IEEE 802.3 compatible Easily interfaced to 8086, 68000, Z8000, LSI-II micro­ processors On-board DMA and buffer management, 48 byte FIFO 24-bit wide linear addressing (Bus Master Mode)