MK5027 Search Results

k5027

Abstract: HDC3 68000 thomson
Contextual Info: n = J SGS-THOMSON * l i I KfflQMtlüKSTMOgi MK5027 SS7 SIGNALLING LINK CONTROLLER . CMOS • FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS . SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE . COMPLETE LEVEL 2 IMPLEMENTATION

DIP48

Abstract: DIP-48 MK5025 MK5027N MK5027Q MK50H25N MK50H25Q MK50H27 MK50H27Q MK50H28N
Contextual Info: TELECOM AND DATA COMMUNICATIONS DATACOM PACKET SWITCHING/CCS#7 Type MK5025 MK50H25Q MK50H25N MK5027Q MK5027N MK50H27 MK50H27Q MK50H28Q MK50H28N MK5029 Description Package X 25 LAPB/ISDN LAPD/HDLC CMOS Hi-Speed Link Level Controller with DMA X 25 Link Level Controller

J 5027 r

Abstract: LD E 5027 BU 5027
Contextual Info: / = Ä 7 T S G S -T H O M S O N # ^ » í m [ i r a M Q MK5027 e s SS7 SIGNALLING LINK CONTROLLER • CMOS ■ FULLY COM PATIBLE W ITH BOTH 8 OR 16 BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATA RATE UP TO 2.5Mbps FO R S S 7 PROTO­ COL PROCESSING , 7Mbps FOR TRANSPAR­

JT-Q703

Abstract: Q703 MK5027 MK50H25 MK50H27 BSNT
Contextual Info: APPLICATION NOTE Upgrading From MK5027 to MK50H27 by Darin Kincaid The MK50H27 is a pin for pin replacement for the MK5027 with additional features and performance enhancements. Options such as TTC JT-Q703 protocol operation, Receive Signal Unit Timer, and

Contextual Info: £ jj SGS-THOMSON ¡HJOTTIfMOOi MK5027 SS7 SIGNALLING LINK CONTROLLER • CMOS . FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATA RATE UP TO 2.5Mbps FOR SS7 PROTO­ COL PROCESSING , 7Mbps FOR TRANSPAR­ ENT HDLC MODE ■ COMPLETE LEVEL 2 IMPLEMENTATION

TSCT 2300

Abstract: 48-PIN DIP48 MK5025 MK5027 PLCC52 Z8000 DALI BASIC SO LSI-11
Contextual Info: MK5027 SS7 SIGNALLING LINK CONTROLLER CMOS FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE COMPLETE LEVEL 2 IMPLEMENTATION COMPATIBLE WITH 1988 CCITT, AT&T,

Contextual Info: 7^2^237 0045434 725 • SGTH SGS-THOMSON MK5027 SS7 SIGNALLING LINK CONTROLLER ■ CMOS ■ FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATA RATE UP TO 2.5Mbps FOR SS7 PROTO­ COL PROCESSING , 7Mbps FOR TRANSPAR­ ENT HDLC MODE

MK68590

Abstract: Mostek MK5027 DAL00 DAL08 68200 MK5025 mostek clock X25 CCITT DAL12
Contextual Info: é M ♦ k THOMSON COMPONENTS MOSTEK A D IR N C IË COMMUNICATION PRODUCTS D N FO R G M ÎiM G O ft! DATA SHEET MK5027 FEATURES VSS-GND DAL07 DAL06 DAL05 DAL04 DALD3 DALO2 DAL01 DAL00 □ CMOS □ Fully com patible with both 8 or 16 bit systems. C System clock rate to 10 M H z.

mk5021

Abstract: DIP-48 DIP48
Contextual Info: TELECOM AND DATA COMMUNICATIONS DATACOM PACKET SWITCHING/CCS#7 Type MK5025 MK50H25Q MK50H25N MK5027Q MK5027N MK50H28Q MK50H28N MK5029 Description Package X 25 LAPB/ISDN LAPD/HDLC CMOS Hi-Speed Link Level Controller with DMA X 25 Link Level Controller X 25 Link Level Controller

JT-Q703

Abstract: Q703 MK50H27 MK5027 MK50H25
Contextual Info: APPLICATION NOTE Upgrading From MK5027 to MK50H27 by Darin Kincaid The MK50H27 is a pin for pin replacement for the MK5027 with additional features and performance enhancements. Options such as TTC JT-Q703 protocol operation, Receive Signal Unit Timer, and

TSCT 2300

Abstract: 48-PIN DIP48 MK5025 MK5027 PLCC52 Z8000 describe with pin diagram of 8088
Contextual Info: MK5027 SS7 SIGNALLING LINK CONTROLLER CMOS FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE COMPLETE LEVEL 2 IMPLEMENTATION COMPATIBLE WITH 1988 CCITT, AT&T,

DALI CONTROL

Abstract: dali MK503 DTR dali
Contextual Info: MK5027 SS7 SIGNALLING LINK CONTROLLER CMOS FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE COMPLETE LEVEL 2 IMPLEMENTATION COMPATIBLE WITH 1988 CCITT, AT&T,

dale r01f

Abstract: MK68H MK68590 r01f dale MK68200 Z8000 MOSTEK ROM r01f mostek MK5025 IN914
Contextual Info: MK5025 P R E L IM IN A R Y C O M M U N IC A T IO N S PR O O U C TS FEATURES DAL04 £ £ 3 £ 4 £ S £ Z Data rate up to 7 MBPS with 64 bytes FIFOs in each direction. DAL03 6 C DA102 7 DAL01 1 H Z Complete Date Link Layer Implementation. DALDQ £ £ 11 £

80386SX

Abstract: DIP48 MK5025 MK5027 MK50H25 Z8000 dali Receiver 80286 instruction
Contextual Info: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst

Contextual Info: MK50H25 HIGH SPEED X.25 LINK LEVEL CONTROLLER PRODUCT PREVIEW • Fully com patible with both 8 or 16 bit systems. ■ System clock rate up to 33 MHz. ■ Data rate up to 20 Mbps continuous or up to 50 Mbps bursted ■ Separate 64-byte Transm it and Receive FIFO.

mk5021

Abstract: N393 BCNT DIP48 MK5027 MK50H28 PLCC52 Z8000 A 1905 LMI
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

PQFP44

Abstract: STLC5432 STLC5432Q PQFP4410X10 8192KB
Contextual Info: / = T S G S -TH O M S O N ^ 7 # . [* ^ Â g T ÏÏ!M STLC5432 []© S 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE PRODUCT PREVIEW ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER(CEPT STANDARD ISDN PRIMARY ACCESS CONTROLLER (COMPATIBLE WITH ETSI, OPTION 1 AND 2)

AN489

Abstract: mk5021 an-490 AN-489 mk5021 technical manual
Contextual Info: ALPHANUMERICAL INDEX ISDN Type Number Function Page GS1T70-D540 ISDN DC-DC Converter 275 ST5080 Piafe Programmable ISDN Audio Front End 245 ST5410 2B1QU Interface Device 27 ST5410 User Manual 81 ST5420 Sid-^W : S/T Interface Device with Microwire/DSI 153 ST5421

mk5021

Abstract: TSW 8088 SRS 4451 DE-A1D
Contextual Info: ^ 7 ^ 7 # « S G S -T H O M S O N IM » iL [Ì g » S l(g § TECHNICAL MANUAL MK5021 SERIAL COMMUNICATIONS CONTROLLER TABLE OF CONTENTS SECTION PAGE SECTION 1 INTRODUCTION Introduction 3 SECTION 2 FEATURES Features 3 SECTION 3 OPERATIONAL DESCRIPTION 3.1 Functional B lo c k s .

STR d 4412 PINS DETAILS

Abstract: dali n39l
Contextual Info: SGS-THOMSON iH lM M O e s M K 5 0 H 2 8 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES • Based on ITU Q.933 Annex A and T1.617 An­ nex D Standards for Frame Relay Service and Additional Pocedures tor Permanent Virtual Circuits PVCs . ■ Optional Transparent Mode (no LMI Protocol

DIP48

Abstract: MK5021 MK5027 MK50H28 PLCC52 Z8000
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER ADVANCE DATA SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent (or no LMI/LIV Protocol

M915

Contextual Info: /T T * li. S G S -IH O M S O N lÄ G M IIL i » « © ! S T LC 5 4 3 2 2Mbit C E P T & PRIM ARY RATE CONTROLLER DEVICE PR ELIM IN A R Y DATA • ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER CEPT STANDARD ■ ISDN PRIMARY ACCESS CONTROLLER (COMPATIBLE WITH ETSI, OPTION 1 AND 2)

uav design specification

Abstract: water filling station circuit diagram DALI CONTROL logical block diagram of 80286 uav electronic design water level controller using timer 555 8086 microprocessor pin description control data bus for 80286 uav design z80 cio
Contextual Info: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst